公开(公告)号：US20160269193A1

公开(公告)日：2016-09-15

申请号：US15063124

申请日：2016-03-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem ZWART ,  John Bruce BOWLERWELL ,  Michael PAGE ,  Alastair BOOMER

IPC: H04L12/40

CPC classification number: H04L12/40013 ,  G06F13/4027 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016 ,  H04L5/1476

Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

Abstract translation: 在由信号总线连接的第一和第二模块之间发送信息的方法包括在第一模块中产生时钟信号，并将时钟信号施加在总线的第一行上。 在所述时钟信号的每个周期的前半个周期期间，第一模式的位值从总线的第二行从第二模块发送到第一模块。 在所述时钟信号的每个周期的后半个周期期间，第二模式的比特值在总线的第二线路上从第一模块发送到第二模块，其中所述时钟信号的每个周期的第二半周期 与所述时钟信号的每个周期的前半个周期不同。 然后可以通过改变比特值的第二模式来将信息从第一模块传送到第二模块; 并且可以通过改变比特值的第一模式从第二模块向第一模块发送信息。

公开(公告)号：US20180176034A1

公开(公告)日：2018-06-21

申请号：US15898839

申请日：2018-02-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem ZWART ,  John Bruce BOWLERWELL ,  Michael PAGE ,  Alastair BOOMER

IPC: H04L12/40 ,  H04L5/14 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L12/40013 ,  G06F13/4027 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016 ,  H04L5/1476

Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.