LOAD DETECTION
    2.
    发明申请
    LOAD DETECTION 审中-公开

    公开(公告)号:US20200186927A1

    公开(公告)日:2020-06-11

    申请号:US16709075

    申请日:2019-12-10

    Abstract: This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.

    LOW POWER BIDIRECTIONAL BUS
    3.
    发明申请
    LOW POWER BIDIRECTIONAL BUS 有权
    低功率双向总线

    公开(公告)号:US20160269193A1

    公开(公告)日:2016-09-15

    申请号:US15063124

    申请日:2016-03-07

    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

    Abstract translation: 在由信号总线连接的第一和第二模块之间发送信息的方法包括在第一模块中产生时钟信号,并将时钟信号施加在总线的第一行上。 在所述时钟信号的每个周期的前半个周期期间,第一模式的位值从总线的第二行从第二模块发送到第一模块。 在所述时钟信号的每个周期的后半个周期期间,第二模式的比特值在总线的第二线路上从第一模块发送到第二模块,其中所述时钟信号的每个周期的第二半周期 与所述时钟信号的每个周期的前半个周期不同。 然后可以通过改变比特值的第二模式来将信息从第一模块传送到第二模块; 并且可以通过改变比特值的第一模式从第二模块向第一模块发送信息。

    CIRCUITRY FOR DETECTING JACK PLUG REMOVAL

    公开(公告)号:US20210167557A1

    公开(公告)日:2021-06-03

    申请号:US16952860

    申请日:2020-11-19

    Abstract: The present disclosure relates to circuitry for detecting at least partial removal of an audio accessory plug from a corresponding socket. The circuitry comprises a monitoring unit comprising a first terminal configured to be electrically connected to a first socket contact of the socket that is in electrical contact with a first plug contact of the plug when the plug is fully received in the socket. The monitoring unit is configured to monitor a first impedance of a first signal path coupled to the first terminal, and the circuitry is configured to output a signal indicative of detection of at least partial removal of the plug from the socket in response to detection by the monitoring unit of a first predetermined sequence of impedance states of the first signal path.

    LOW POWER BIDIRECTIONAL BUS
    5.
    发明申请

    公开(公告)号:US20180176034A1

    公开(公告)日:2018-06-21

    申请号:US15898839

    申请日:2018-02-19

    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

    LOAD DETECTION
    6.
    发明申请

    公开(公告)号:US20220060832A1

    公开(公告)日:2022-02-24

    申请号:US17516830

    申请日:2021-11-02

    Abstract: This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.

    SOCKET MONITORING
    7.
    发明申请
    SOCKET MONITORING 审中-公开

    公开(公告)号:US20200309865A1

    公开(公告)日:2020-10-01

    申请号:US16899212

    申请日:2020-06-11

    Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.

    SOCKET MONITORING
    8.
    发明申请
    SOCKET MONITORING 审中-公开

    公开(公告)号:US20190128949A1

    公开(公告)日:2019-05-02

    申请号:US16164478

    申请日:2018-10-18

    Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.

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