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    DIGITAL ACCESSORY INTERFACE
    4.
    发明申请
    DIGITAL ACCESSORY INTERFACE 审中-公开

    公开(公告)号：US20180102894A1

    公开(公告)日：2018-04-12

    申请号：US15840592

    申请日：2017-12-13

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Willem ZWART

    IPC: H04L5/16 ,  H04L7/00

    CPC classification number: H04L5/16 ,  H04L7/0008

    Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

    DETECTION OF A MALICIOUS ATTACK
    5.
    发明申请
    DETECTION OF A MALICIOUS ATTACK 审中-公开

    公开(公告)号：US20190267009A1

    公开(公告)日：2019-08-29

    申请号：US15906308

    申请日：2018-02-27

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Willem ZWART

    IPC: G10L17/06 ,  G10L17/22 ,  G10L21/0316 ,  G06F21/32 ,  G06F21/56

    Abstract: According to embodiments described herein there is provided methods and apparatus for authenticating a first audio signal received at a device. The method comprises receiving the first audio signal at a first input, wherein the first input is for receiving audio signals from a first microphone, receiving a second audio signal at a second input from a second microphone; and comparing a third audio signal derived from the first audio signal to a fourth audio signal derived from the second audio signal. The method further comprises determining, based on the comparison, whether the first audio signal and the second audio signal meet a predetermined condition, wherein the predetermined condition indicates that the first audio signal and the second audio signal are both derived from a common acoustic signal; and using the first audio signal as an input to a voice biometrics module responsive to a determination that the first audio signal and the second audio signal meet the condition.

    LOW POWER BIDIRECTIONAL BUS
    6.
    发明申请
    LOW POWER BIDIRECTIONAL BUS 有权
    低功率双向总线

    公开(公告)号：US20160269193A1

    公开(公告)日：2016-09-15

    申请号：US15063124

    申请日：2016-03-07

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Willem ZWART ,  John Bruce BOWLERWELL ,  Michael PAGE ,  Alastair BOOMER

    IPC: H04L12/40

    CPC classification number: H04L12/40013 ,  G06F13/4027 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016 ,  H04L5/1476

    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

    Abstract translation: 在由信号总线连接的第一和第二模块之间发送信息的方法包括在第一模块中产生时钟信号，并将时钟信号施加在总线的第一行上。 在所述时钟信号的每个周期的前半个周期期间，第一模式的位值从总线的第二行从第二模块发送到第一模块。 在所述时钟信号的每个周期的后半个周期期间，第二模式的比特值在总线的第二线路上从第一模块发送到第二模块，其中所述时钟信号的每个周期的第二半周期 与所述时钟信号的每个周期的前半个周期不同。 然后可以通过改变比特值的第二模式来将信息从第一模块传送到第二模块; 并且可以通过改变比特值的第一模式从第二模块向第一模块发送信息。

    COMMUNICATION CIRCUITRY AND CONTROL CIRCUITRY THEREOF
    7.
    发明申请
    COMMUNICATION CIRCUITRY AND CONTROL CIRCUITRY THEREOF 审中-公开

    公开(公告)号：US20190334756A1

    公开(公告)日：2019-10-31

    申请号：US15966631

    申请日：2018-04-30

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Alastair Mark BOOMER ,  Erich Paul ZWYSSIG ,  Gavin Alexander WAITE ,  Willem ZWART

    IPC: H04L12/24 ,  H04J3/06 ,  H04L7/00

    Abstract: Communication circuitry, comprising: N communication nodes being clock-candidate nodes, where N≥2; N communication units for communication using respective communication protocols, and connected or connectable to receive respective clock signals for communication under their respective communication protocols via respective said clock-candidate nodes; and a control unit configured, in a decision operation, to monitor the clock-candidate nodes and decide which of the communication protocols is in use dependent on at which of the clock-candidate nodes a received clock signal is detected, wherein at least one said communication unit is connected or connectable to receive and/or transmit data under its respective communication protocol via at least one said clock-candidate node other than the clock-candidate node via which that communication unit is to receive its respective clock signal.

    DIGITAL ACCESSORY INTERFACE
    8.
    发明申请
    DIGITAL ACCESSORY INTERFACE 审中-公开

    公开(公告)号：US20180309564A1

    公开(公告)日：2018-10-25

    申请号：US16021793

    申请日：2018-06-28

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Willem ZWART

    IPC: H04L5/16 ,  H04L7/00

    CPC classification number: H04L5/16 ,  H04L7/0008

    Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

    DIGITAL ACCESSORY INTERFACE CALIBRATION
    9.
    发明申请
    DIGITAL ACCESSORY INTERFACE CALIBRATION 审中-公开

    公开(公告)号：US20180067715A1

    公开(公告)日：2018-03-08

    申请号：US15798608

    申请日：2017-10-31

    Applicant: Cirrus Logic International Semiconductor Ltd.

    Inventor： Willem ZWART

    IPC: G06F3/16 ,  G06F13/38

    CPC classification number: G06F3/165 ,  G06F13/385

    Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory. In the device, timings of said second signal level transitions as received at said device are determined relative to the master transmission clock, and timing delay control data based on said determination is transmitted from the device to the accessory. In the accessory, the timing delay control data is received, and the stored delay value is updated based on the timing delay control data.

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