公开(公告)号：US09935786B2

公开(公告)日：2018-04-03

申请号：US15063124

申请日：2016-03-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart ,  John Bruce Bowlerwell ,  Michael Page ,  Alastair Boomer

IPC: H04L12/40 ,  H04L5/14 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4027 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016 ,  H04L5/1476

Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

公开(公告)号：US10218535B2

公开(公告)日：2019-02-26

申请号：US15898839

申请日：2018-02-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart ,  John Bruce Bowlerwell ,  Michael Page ,  Alastair Boomer

IPC: H04L5/14 ,  H04L12/40 ,  G06F13/42 ,  G06F13/40

Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.