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公开(公告)号：US11653150B2
公开(公告)日：2023-05-16
申请号：US17516830
申请日：2021-11-02
Inventor： John Paul Lesso , Mark James McCloy-Stevens , John Bruce Bowlerwell , Yanto Suryono , Xin Zhao , Morgan Timothy Prior
CPC classification number: H04R5/04 , H03F3/183 , H03G3/3005 , H04R5/02 , H04R29/001 , H04S1/007 , H03G2201/103
Abstract: This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.
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公开(公告)号：US10218535B2
公开(公告)日：2019-02-26
申请号：US15898839
申请日：2018-02-19
Inventor： Willem Zwart , John Bruce Bowlerwell , Michael Page , Alastair Boomer
Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
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公开(公告)号：US11206487B2
公开(公告)日：2021-12-21
申请号：US16709075
申请日：2019-12-10
Inventor： John Paul Lesso , Mark James Mccloy-Stevens , John Bruce Bowlerwell , Yanto Suryono , Xin Zhao , Morgan Timothy Prior
Abstract: This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.
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Patent Agency Ranking
公开(公告)号：US10725121B2
公开(公告)日：2020-07-28
申请号：US16164478
申请日：2018-10-18
Inventor： John Bruce Bowlerwell
Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.
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公开(公告)号：US12041434B2
公开(公告)日：2024-07-16
申请号：US18296266
申请日：2023-04-05
Inventor： John Paul Lesso , Mark James Mccloy-Stevens , John Bruce Bowlerwell , Yanto Suryono , Xin Zhao , Morgan Timothy Prior
CPC classification number: H04R5/04 , H03F3/183 , H03G3/3005 , H04R5/02 , H04R29/001 , H04S1/007 , H03G2201/103
Abstract: This application relates to audio driving circuitry (100), and in particular to audio driving circuitry for outputting first and second audio driving signals for driving a stereo audio load (106), which may be a stereo audio load of an accessory apparatus (102) removably coupled to the audio driving circuitry in use. A load monitor (111) is provided for monitoring to monitor, from a monitoring node (112), an indication of a common mode return current passing through a common return path, together with an indication of a common mode component of the first and second audio driving signals and to determine an impedance characteristic of the stereo audio load. The load monitor (111) can provide dynamic monitoring of any significant change in load impedance. In some embodiments the load monitor (111) comprises an adaptive filter (301) which adapts a parameter of the filter which is related to the load impedance so as to determine the indication of load impedance.
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公开(公告)号：US11362467B2
公开(公告)日：2022-06-14
申请号：US16952860
申请日：2020-11-19
Inventor： John Bruce Bowlerwell , John Anthony Breslin
IPC: H01R13/66 , G01R31/69 , H01R13/641 , H01R24/58 , H01R107/00
Abstract: The present disclosure relates to circuitry for detecting at least partial removal of an audio accessory plug from a corresponding socket. The circuitry comprises a monitoring unit comprising a first terminal configured to be electrically connected to a first socket contact of the socket that is in electrical contact with a first plug contact of the plug when the plug is fully received in the socket. The monitoring unit is configured to monitor a first impedance of a first signal path coupled to the first terminal, and the circuitry is configured to output a signal indicative of detection of at least partial removal of the plug from the socket in response to detection by the monitoring unit of a first predetermined sequence of impedance states of the first signal path.
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公开(公告)号：US11435412B2
公开(公告)日：2022-09-06
申请号：US16899212
申请日：2020-06-11
Inventor： John Bruce Bowlerwell
Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.
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公开(公告)号：US09935786B2
公开(公告)日：2018-04-03
申请号：US15063124
申请日：2016-03-07
Inventor： Willem Zwart , John Bruce Bowlerwell , Michael Page , Alastair Boomer
CPC classification number: H04L12/40013 , G06F13/4027 , G06F13/4282 , G06F13/4291 , G06F2213/0016 , H04L5/1476
Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
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