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公开(公告)号：US20190257866A1
公开(公告)日：2019-08-22
申请号：US16121259
申请日：2018-09-04
Inventor： Gautham S. SIVASANKAR , Tejasvi DAS , Emmanuel MARCHAIS , Amar VELLANKI , Leyi YIN , John L. MELANSON , Venugopal CHOUKINISHI
Abstract: A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.
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公开(公告)号：US20200274548A1
公开(公告)日：2020-08-27
申请号：US16795045
申请日：2020-02-19
Inventor： Leyi YIN , John L. MELANSON
Abstract: A system may include a modulator configured to generate a modulated data stream of samples from an input signal wherein each value of data in the modulated data stream when encoded is represented by a multi-bit code, wherein the modulator comprises a quantizer configured to quantize the modulated data stream from the input signal and feed back the modulated data stream as a feedback signal to an input of the modulator and a memory configured to store one or more samples of the modulated data stream. The system may also include an encoder configured to generate a synchronized serialized code stream from the modulated data stream. The quantizer may be configured to, based on the one or more samples of the modulated data stream stored in the memory, constrain the modulated data stream such that a synchronization state of the synchronized serialized code stream generated by the encoder is determinable based on the synchronized serialized code stream.
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公开(公告)号：US20210175896A1
公开(公告)日：2021-06-10
申请号：US16945520
申请日：2020-07-31
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Leyi YIN
Abstract: A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.
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公开(公告)号：US20210175895A1
公开(公告)日：2021-06-10
申请号：US16945288
申请日：2020-07-31
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Leyi YIN
Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.
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