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公开(公告)号：US20200343871A1
公开(公告)日：2020-10-29
申请号：US16928444
申请日：2020-07-14
Inventor： Johann G. GABORIAU , David M. OLIVENBAUM , Xiaofan FEI , Amar VELLANKI , Venugopal CHOUKINISHI , Gautham SIVASANKAR , Wai-Shun SHUM
Abstract: A method for calibrating gain in a multi-path subsystem having a first processing path, a second processing path, and a mixed signal return path, may include low-pass filtering an input signal and a mixed signal return path signal generated from the input signal at subsonic frequencies to generate a filtered input signal and a filtered mixed signal return path signal and tracking and correcting for a gain difference between the first processing path and the second processing path based on the filtered input signal and the filtered mixed signal return path signal.
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Patent Agency Ranking
2.发明公开公开(公告)号：US20230379592A1
公开(公告)日：2023-11-23
申请号：US18318896
申请日：2023-05-17
Inventor： Wai-Shun SHUM , Amar VELLANKI , Jeffrey SKARZYNSKI , Gautham S. SIVASANKAR , Xingdong DAI , Venugopal CHOUKINISHI , Xiaofan FEI , Xin ZHAO
IPC: H04N23/90
CPC classification number: H04N23/90
Abstract: A system for relaying communication for a PHY/data link level communication protocol may include a first device having a first and second transceiver, the first transceiver having a first protocol controller configured to detect a first bus condition and second transceiver having a second protocol controller configured to detect a second bus condition and a switching matrix coupled to the first and second transceiver and configured to operate in a relaying mode to enable: the first protocol controller to control a physical layer of the second transceiver and enables the second protocol controller to control a physical layer of the first transceiver, a physical layer of a first transmitter of the first transceiver to receive an output of a second receiver of the second transceiver, and the physical layer of a second transmitter of the second transceiver to receive an output of a first receiver of the first transceiver.
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公开(公告)号：US20240187205A1
公开(公告)日：2024-06-06
申请号：US18471856
申请日：2023-09-21
Inventor： Jeffrey SKARZYNSKI , Wai-Shun SHUM , Amar VELLANKI , Venugopal CHOUKINISHI , Xin ZHAO , John L. MELANSON
CPC classification number: H04L7/033 , H04J3/0688
Abstract: A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.
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公开(公告)号：US20210175322A1
公开(公告)日：2021-06-10
申请号：US17019621
申请日：2020-09-14
Inventor： John L. MELANSON , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Johann G. GABORIAU
IPC: H01L49/02 , H01L23/522 , H03F1/02
Abstract: A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.
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公开(公告)号：US20210175896A1
公开(公告)日：2021-06-10
申请号：US16945520
申请日：2020-07-31
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Leyi YIN
Abstract: A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.
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公开(公告)号：US20210175895A1
公开(公告)日：2021-06-10
申请号：US16945288
申请日：2020-07-31
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Leyi YIN
Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.
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