公开(公告)号：US08982136B2

公开(公告)日：2015-03-17

申请号：US13108657

申请日：2011-05-16

Applicant: Maurice Ribble ,  Colin Sharp ,  Jeffrey Leger

Inventor： Maurice Ribble ,  Colin Sharp ,  Jeffrey Leger

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: This disclosure describes techniques for automatically selecting a rendering mode for use by a graphics processing unit (GPU) to render graphics data for display. More specifically, the techniques include evaluating at least two metrics associated with rendering graphics data of one or more rendering units, and automatically selecting either an immediate rendering mode or a deferred rendering mode for a current rendering unit based on the evaluated metrics. The selected rendering mode may be the one of the rendering modes predicted to use less power and/or system bandwidth to render the graphics data of the current rendering unit. A rendering unit may comprise a set of frames, a frame, a portion of a frame, multiple render targets associated with a frame, a single render target associated with a frame, or a portion of a single render target.

Abstract translation: 本公开描述了用于自动选择渲染模式以供图形处理单元（GPU）使用以呈现用于显示的图形数据的技术。 更具体地说，这些技术包括评估与渲染一个或多个渲染单元的图形数据相关联的至少两个度量，并且基于评估的度量自动选择当前渲染单元的立即渲染模式或延迟渲染模式。 所选择的渲染模式可以是被预测为使用较少功率和/或系统带宽来渲染当前渲染单元的图形数据的渲染模式之一。 渲染单元可以包括一组帧，帧，帧的一部分，与帧相关联的多个渲染目标，与帧相关联的单个渲染目标或单个渲染目标的一部分。

公开(公告)号：US06850244B2

公开(公告)日：2005-02-01

申请号：US09759789

申请日：2001-01-11

Applicant: Aaftab Munshi ,  Colin Sharp

Inventor： Aaftab Munshi ,  Colin Sharp

IPC: G06F3/14 ,  G06T15/04 ,  G09G5/393 ,  G09G5/395 ,  G06T15/00

CPC classification number: G06T15/04 ,  G06F3/14 ,  G09G5/363 ,  G09G5/393 ,  G09G5/395

Abstract: A method and system for providing surface texture in a graphics image rendered by a graphics processing system. Color values of a pixel having a normal vector normal to a surface in which the pixel is located are calculated based on a perturbed normal vector. The perturbed normal vector is displaced from the normal vector by a displacement equal to the sum of a first vector tangent to the surface at the location of the pixel scaled by a first scale factor and a first displacement value, and a second vector tangent to the surface at the location of the pixel and scaled by a second scale factor and a second displacement value, the second vector perpendicular to the first vector. The displacement values are representative of partial derivatives of a function defining a texture applied to the surface and the scale factors are used to scale the magnitude of the resulting perturbed normal. The color value for the pixel being rendered will be based on the perturbed normal vector instead of the normal vector.

Abstract translation: 一种用于在由图形处理系统呈现的图形图像中提供表面纹理的方法和系统。 基于扰动的法向量计算具有与像素所在的表面垂直的法线矢量的像素的颜色值。 扰动法线向量从法向量移位一个位移，该位移等于第一个矢量与在第一比例因子和第一位移值之间缩放的像素的位置处的表面切线的和， 表面在像素的位置处并且由第二比例因子和第二位移值缩放，第二矢量垂直于第一矢量。 位移值表示定义应用于表面的纹理的函数的偏导数，并且比例因子用于缩放所得到的扰动法线的幅度。 正在渲染的像素的颜色值将基于扰动的法向量而不是法向量。

公开(公告)号：US20120293519A1

公开(公告)日：2012-11-22

申请号：US13108657

申请日：2011-05-16

Applicant: Maurice Ribble ,  Colin Sharp ,  Jeffrey Leger

Inventor： Maurice Ribble ,  Colin Sharp ,  Jeffrey Leger

IPC: G06T1/00

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: This disclosure describes techniques for automatically selecting a rendering mode for use by a graphics processing unit (GPU) to render graphics data for display. More specifically, the techniques include evaluating at least two metrics associated with rendering graphics data of one or more rendering units, and automatically selecting either an immediate rendering mode or a deferred rendering mode for a current rendering unit based on the evaluated metrics. The selected rendering mode may be the one of the rendering modes predicted to use less power and/or system bandwidth to render the graphics data of the current rendering unit. A rendering unit may comprise a set of frames, a frame, a portion of a frame, multiple render targets associated with a frame, a single render target associated with a frame, or a portion of a single render target.

Abstract translation: 本公开描述了用于自动选择渲染模式以供图形处理单元（GPU）使用以呈现用于显示的图形数据的技术。 更具体地说，这些技术包括评估与渲染一个或多个渲染单元的图形数据相关联的至少两个度量，并且基于评估的度量自动选择当前渲染单元的立即渲染模式或延迟渲染模式。 所选择的渲染模式可以是被预测为使用较少功率和/或系统带宽来渲染当前渲染单元的图形数据的渲染模式之一。 渲染单元可以包括一组帧，帧，帧的一部分，与帧相关联的多个渲染目标，与帧相关联的单个渲染目标或单个渲染目标的一部分。

公开(公告)号：US20120206466A1

公开(公告)日：2012-08-16

申请号：US13024579

申请日：2011-02-10

Applicant: Colin Sharp ,  Zachary Aaron Pfeffer ,  Eduardus A. Metz ,  Maurice Ribble

Inventor： Colin Sharp ,  Zachary Aaron Pfeffer ,  Eduardus A. Metz ,  Maurice Ribble

IPC: G06F12/02

CPC classification number: G06T1/60 ,  G06F3/064 ,  G06F12/0802

Abstract: In general, aspects of this disclosure describe example techniques for efficient storage of data of various data types for graphics processing. In some examples, a processing unit may assign first and second contiguous range of addresses for a first and second data type, respectively. The processing unit may store at least one of graphics data of the first or second data type or addresses of the graphics data of the first or second data type within blocks whose addresses are within the first and second contiguous range of addresses, respectively. The processing unit may store, in cache lines of a cache, the graphics data of the first data type, and the graphics data of the second data type.

Abstract translation: 通常，本公开的方面描述了用于图形处理的各种数据类型的数据的有效存储的示例技术。 在一些示例中，处理单元可以分别为第一和第二数据类型分配第一和第二连续的地址范围。 处理单元可分别存储第一或第二数据类型的图形数据或第一或第二数据类型的图形数据的地址中的至少一个，其地址分别在地址的第一和第二连续范围内的块内。 处理单元可以在高速缓存的高速缓存行中存储第一数据类型的图形数据和第二数据类型的图形数据。

公开(公告)号：US20050182841A1

公开(公告)日：2005-08-18

申请号：US10639810

申请日：2003-08-11

Applicant: Colin Sharp

Inventor： Colin Sharp

IPC: G06F15/16 ,  H04L29/06

CPC classification number: H04L69/16 ,  H04L69/12 ,  H04L69/161 ,  Y10S707/99933

Abstract: A TCP/IP offload network interface device (NID) receives packets from a plurality of clients and generates, from the socket address of each such packet, a hash value. Each hash value identifies one of a plurality of hash buckets maintained on the NID. In a file server, certain socket address bits of the packets are low entropy bits in that they tend to be the same, regardless of which client sent the packet. Others of the socket address bits are high entropy bits. The hash function employed is such that the hash values resulting from the changing values of the high entropy bits are substantially evenly distributed among the plurality of hash buckets. In a fast-path, the NID uses a first hash function to identify TCBs on the NID. In a slow-path, the NID generates a second hash using a second hash function and a host stack uses the second hash.

Abstract translation: TCP / IP卸载网络接口设备（NID）从多个客户端接收分组，并从每个这样的分组的套接字地址生成哈希值。 每个散列值标识在NID上维护的多个散列桶中的一个。 在文件服务器中，数据包的某些套接字地址位是低熵位，因为它们往往是相同的，而不管哪个客户端发送数据包。 插座地址位中的其他位是高熵位。 采用的散列函数使得由高熵比特的变化值产生的散列值在多个散列桶之间基本均匀地分布。 在快速路径中，NID使用第一个散列函数来标识NID上的TCB。 在慢路径中，NID使用第二散列函数生成第二散列，主机栈使用第二散列。

公开(公告)号：US09804995B2

公开(公告)日：2017-10-31

申请号：US13007333

申请日：2011-01-14

Applicant: Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

Inventor： Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

IPC: G06F15/00 ,  G06F15/76 ,  G06F15/173

CPC classification number: G06F15/17325

Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

公开(公告)号：US09047686B2

公开(公告)日：2015-06-02

申请号：US13024579

申请日：2011-02-10

Applicant: Colin Sharp ,  Zachary Aaron Pfeffer ,  Eduardus A. Metz ,  Maurice Ribble

Inventor： Colin Sharp ,  Zachary Aaron Pfeffer ,  Eduardus A. Metz ,  Maurice Ribble

IPC: G09G5/36 ,  G06T9/00 ,  G09G5/39 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F21/00 ,  G06F9/26 ,  G06T1/60 ,  G06F3/06 ,  G06F12/08

CPC classification number: G06T1/60 ,  G06F3/064 ,  G06F12/0802

Abstract: In general, aspects of this disclosure describe example techniques for efficient storage of data of various data types for graphics processing. In some examples, a processing unit may assign first and second contiguous range of addresses for a first and second data type, respectively. The processing unit may store at least one of graphics data of the first or second data type or addresses of the graphics data of the first or second data type within blocks whose addresses are within the first and second contiguous range of addresses, respectively. The processing unit may store, in cache lines of a cache, the graphics data of the first data type, and the graphics data of the second data type.

Abstract translation: 通常，本公开的方面描述了用于图形处理的各种数据类型的数据的有效存储的示例技术。 在一些示例中，处理单元可以分别为第一和第二数据类型分配第一和第二连续的地址范围。 处理单元可分别存储第一或第二数据类型的图形数据或第一或第二数据类型的图形数据的地址中的至少一个，其地址分别在地址的第一和第二连续范围内的块内。 处理单元可以在高速缓存的高速缓存行中存储第一数据类型的图形数据和第二数据类型的图形数据。

公开(公告)号：US20120185671A1

公开(公告)日：2012-07-19

申请号：US13007333

申请日：2011-01-14

Applicant: Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

Inventor： Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

IPC: G06F9/38

CPC classification number: G06F15/17325

Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

Abstract translation: 本公开描述了用于利用并行处理单元来扩展通用图形处理单元（GPGPU）的架构以允许基于流水线的应用的有效处理的技术。 这些技术包括配置连接到作为处理流水线的阶段的并行处理单元的本地存储器缓冲器，以保持用于在并行处理单元之间传送的数据。 本地存储缓冲器允许并行处理单元之间的片上，低功耗，直接数据传输。 本地存储器缓冲器可以包括基于硬件的数据流控制机制，以使得能够在并行处理单元之间传送数据。 以这种方式，数据可以经由本地存储器缓冲器直接从一个并行处理单元传递到处理流水线中的下一个并行处理单元，实际上将并行处理单元转换成一系列流水线级。

公开(公告)号：US20080040519A1

公开(公告)日：2008-02-14

申请号：US11799720

申请日：2007-05-01

Applicant: Daryl Starr ,  Clive Philbrick ,  Colin Sharp

Inventor： Daryl Starr ,  Clive Philbrick ,  Colin Sharp

IPC: G06F3/00

CPC classification number: H04L69/16 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9063 ,  H04L69/161 ,  H04L69/163

Abstract: A 10 Gb/s network interface device offloads TCP/IP datapath functions. Frames without IP datagrams are processed as with a non-offload NIC. Receive frames are filtered, then transferred to preallocated receive buffers within host memory. Outbound frames are retrieved from host memory, then transmitted. Frames with IP datagrams without TCP segments are transmitted without any protocol offload, but received frames are parsed and checked for protocol errors, including checksum accumulation for UDP segments. Receive frames without datagram errors are passed to the host and error frames are dumped. Frames with Tcp segments are parsed and error-checked. Hardware checking is performed for ownership of the socket state. TCP/IP frames which fail the ownership test are passed to the host system with a parsing summary. TCP/IP frames which pass the ownership test are processed by a finite state machine implemented by the CPU. TCP/IP frames for non-owned sockets are supported with checksum accumulation/insertion.

Abstract translation: 10 Gb / s网络接口设备卸载TCP / IP数据路径功能。 没有IP数据报的帧与非卸载NIC一样处理。 接收帧被过滤，然后传输到主机内存中的预先分配的接收缓冲区。 出站帧从主机内存中检索，然后发送。 在没有任何协议卸载的情况下传输具有不带TCP段的IP数据报的帧，但是对于接收的帧进行解析并检查协议错误，包括UDP段的校验和累积。 没有数据报错误的接收帧被传递给主机，并且丢弃错误帧。 具有Tcp段的帧被解析并进行错误检查。 对套接字状态的所有权执行硬件检查。 将所有权测试失败的TCP / IP帧传递到具有解析摘要的主机系统。 通过所有权测试的TCP / IP帧由CPU实现的有限状态机处理。 校验和累积/插入支持非拥有套接字的TCP / IP帧。