公开(公告)号：US20140245249A1

公开(公告)日：2014-08-28

申请号：US14186895

申请日：2014-02-21

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/50

CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器求解离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。

公开(公告)号：US20130144925A1

公开(公告)日：2013-06-06

申请号：US13678266

申请日：2012-11-15

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/10

CPC classification number: G06F17/10 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。

公开(公告)号：US09026574B2

公开(公告)日：2015-05-05

申请号：US13678266

申请日：2012-11-15

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06G7/32 ,  G06F17/00 ,  G06N5/00 ,  G06F17/10 ,  G06F17/11 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F17/10 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。

公开(公告)号：US09405876B2

公开(公告)日：2016-08-02

申请号：US14186895

申请日：2014-02-21

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/50 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。

公开(公告)号：US20130217580A1

公开(公告)日：2013-08-22

申请号：US13707210

申请日：2012-12-06

Applicant: D-Wave Systems Inc.

Inventor： Murray C. Thom ,  Sergey Uchaykin ,  Thomas Mahon ,  David Pires ,  Peter Spear ,  Jacob Craig Petroff

IPC: H01P1/202

CPC classification number: H01P1/202

Abstract: Adaptations and improvements to tubular metal powder filters include employing non-circular cross sectional geometries, aligning the inner conductor off-axis, replacing the inner conductive wire with a conductive trace carried on a printed circuit board, combining multiple filters within a single common outer conductive housing, and employing meandering and other non-parallel signal paths. The various adaptations and improvements are designed to accommodate single-ended and differential signaling, as well as superconducting and non-superconducting applications.

Abstract translation: 对管状金属粉末过滤器的适应和改进包括采用非圆形横截面几何形状，将内部导体对准轴线，将导电线替换为承载在印刷电路板上的导电迹线，将多个过滤器组合在单个共同外部导电 住房和采用曲折和其他非平行信号路径。 各种适应和改进旨在适应单端和差分信号，以及超导和非超导应用。

公开(公告)号：US08670809B2

公开(公告)日：2014-03-11

申请号：US13707210

申请日：2012-12-06

Applicant: D-Wave Systems Inc.

Inventor： Murray C. Thom ,  Sergey Uchaykin ,  Thomas Mahon ,  David Pires ,  Peter Spear ,  Jacob Craig Petroff

IPC: H01L39/24

CPC classification number: H01P1/202

Abstract: Adaptations and improvements to tubular metal powder filters include employing cross sectional geometries of any suitable shape, aligning the inner conductor off-axis, replacing the inner conductive wire with a conductive trace or a superconductive trace carried by a printed circuit board, combining multiple filters within a single common outer conductive housing, and employing meandering and other non-parallel signal paths. The various adaptations and improvements are designed to accommodate single-ended and differential signaling, as well as superconducting and non-superconducting applications.

Abstract translation: 管状金属粉末过滤器的适应和改进包括采用任何合适形状的横截面几何形状，将内部导体对准轴线，用导电迹线或由印刷电路板承载的超导迹线替换内部导线，将多个滤波器组合在一起 单个公共外部导电外壳，并采用曲折和其他非平行信号路径。 各种适应和改进旨在适应单端和差分信号，以及超导和非超导应用。