公开(公告)号：US09026574B2

公开(公告)日：2015-05-05

申请号：US13678266

申请日：2012-11-15

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06G7/32 ,  G06F17/00 ,  G06N5/00 ,  G06F17/10 ,  G06F17/11 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F17/10 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。

公开(公告)号：US09405876B2

公开(公告)日：2016-08-02

申请号：US14186895

申请日：2014-02-21

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/50 ,  G06N99/00 ,  B82Y10/00

CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。

公开(公告)号：US09875215B2

公开(公告)日：2018-01-23

申请号：US14109657

申请日：2013-12-17

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Aidan Patrick Roy

IPC: G06F17/10 ,  G06N99/00

CPC classification number: G06F17/10 ,  G06N99/002

Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.

公开(公告)号：US20140324933A1

公开(公告)日：2014-10-30

申请号：US14109657

申请日：2013-12-17

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Aidan Patrick Roy

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06N99/002

Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.

Abstract translation: 系统和方法通过使用硬件图分解的量子处理器来解决问题。 原始图形的分解可以基于硬件特定图形建立在第一阶段中，并且在第二阶段通过例如从分解中去除顶点来进行细化。 硬件特定图可以是特定于一块硬件的图，例如包括多个量子位和可耦合器的量子处理器，其可操作地通信地耦合成对的量子位。

公开(公告)号：US20140245249A1

公开(公告)日：2014-08-28

申请号：US14186895

申请日：2014-02-21

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/50

CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器求解离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是布尔逻辑电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 量子处理器可以包括多组量子位，每组量子位耦合到相应的退火信号线，使得每组量子位的动态演化独立于其他量子位集合的动态演化被控制。

公开(公告)号：US20130144925A1

公开(公告)日：2013-06-06

申请号：US13678266

申请日：2012-11-15

Applicant: D-Wave Systems Inc.

Inventor： William Macready ,  Geordie Rose ,  Thomas Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/10

CPC classification number: G06F17/10 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract translation: 解决计算问题可能包括生成计算问题的逻辑电路表示，将逻辑电路表示编码为离散优化问题，以及使用量子处理器来解决离散优化问题。 可以钳位逻辑电路表示的输出，使得解决方案涉及有效地执行逻辑电路表示，以确定对应于被钳位的输出的输入。 该表示可以是乘法电路。 离散优化问题可以由一组微型优化问题组成，其中每个微型优化问题从逻辑电路表示编码相应的逻辑门。 乘法电路可以采用因子的二进制表示，并且这些二进制表示可以被分解以减少表示乘法电路所需的变量的总数。