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    Power delivery analysis and design
    4.
    发明授权
    Power delivery analysis and design 有权
    电力分配和设计

    公开(公告)号：US08055486B2

    公开(公告)日：2011-11-08

    申请号：US12187164

    申请日：2008-08-06

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.

    摘要翻译： 提供计算机程序产品用于分层系统的功率传递分析和设计。 该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。 该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层 列表。 该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

    System DC Analysis Methodology
    6.
    发明授权
    System DC Analysis Methodology 有权
    系统直流分析方法

    公开(公告)号：US07460986B2

    公开(公告)日：2008-12-02

    申请号：US11380058

    申请日：2006-04-25

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    IPC分类号： G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5036

    摘要： A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.

    摘要翻译： 提供了一种用于分层系统的功率传递分析和设计的方法。 该方法包括建立与分级系统的每个元素相对应的模型，编译包含对应于分层系统的每个元素的模型的存储库，其中存储库包括网络列表，域列表，组件列表，引脚列表 ，和一个图层列表。 该方法还包括对分层系统的每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化，以及从存储库中包含的模型组装系统模型。 此外，该方法包括通过将系统模型转换为完全由电阻组成的扁平化系统模型，并在扁平化系统模型上运行模拟来平坦化系统模型。

    Fabricating substrates having low inductance via arrangements
    7.
    发明授权
    Fabricating substrates having low inductance via arrangements 失效
    通过布置制造具有低电感的基板

    公开(公告)号：US07614141B2

    公开(公告)日：2009-11-10

    申请号：US11355713

    申请日：2006-02-16

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

    IPC分类号： H01K3/10

    CPC分类号： H05K1/162 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09609 ,  H05K2201/09627 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00

    摘要： A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

    摘要翻译： 提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。 通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。 这种减少是通过引入T-jogs和附加通孔来实现的。 这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。 在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。 这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

    SYSTEM DC ANALYSIS METHODOLOGY
    8.
    发明申请
    SYSTEM DC ANALYSIS METHODOLOGY 有权
    系统直流分析方法

    公开(公告)号：US20080294414A1

    公开(公告)日：2008-11-27

    申请号：US12187164

    申请日：2008-08-06

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao Gia-Harvey Truong ,  Roger D. Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.

    摘要翻译： 提供计算机程序产品用于分层系统的功率传递分析和设计。 该产品包括可由处理电路读取的存储介质，用于存储由处理电路执行以便于方法的指令。 该方法包括构建与分级系统的每个元素相对应的模型，以及编译包含与每个元素对应的模型的仓库，其中仓库包括网络列表，域列表，组件列表，引脚列表和层 列表。 该方法还包括对每个元素，网络列表，域列表，组件列表，引脚列表和层列表执行优化的网格化; 从存储库中包含的模型组装系统模型; 通过将系统模型转换为完全由电阻组成的扁平化系统模型来平坦化系统模型; 并在扁平化系统模型上运行模拟。

    Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing
    9.
    发明申请
    Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing 失效
    通过基于电压检测的截止执行单元来缓解电源噪声响应

    公开(公告)号：US20070283172A1

    公开(公告)日：2007-12-06

    申请号：US11420820

    申请日：2006-05-30

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26

    摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

    摘要翻译： 提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。 感测单元感测电路的电压。 感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。 响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

    Apparatus and method for selectively monitoring multiple voltages in an IC or other electronic chip
    10.
    发明授权
    Apparatus and method for selectively monitoring multiple voltages in an IC or other electronic chip 失效
    用于选择性地监测IC或其他电子芯片中的多个电压的装置和方法

    公开(公告)号：US07469199B2

    公开(公告)日：2008-12-23

    申请号：US11278848

    申请日：2006-04-06

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    IPC分类号： G06F11/00

    CPC分类号： G01R19/16552

    摘要： An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.

    摘要翻译： 提供了一种用于监视分区电子芯片的多个电压域的每个域中可用电压的装置和方法。 该装置包括耦合到芯片的单个导电链路，并且还包括具有单个输出和多个可切换输入的域选择网络，该输出连接到单个导电链路，并且两个输入端被连接以监视相应的电压电平 的多个电压域中的两个。 设置控制机构以操作选择网络，以便选择性地将输入中的一个连接到单个导电链路，并且连接到电子芯片外部的传感器装置以测量所监测的多个 电压域使用单个导电链路。