公开(公告)号：US12131985B2

公开(公告)日：2024-10-29

申请号：US17470519

申请日：2021-09-09

Applicant: CORNING INCORPORATED

Inventor： Mandakini Kanungo ,  Prantik Mazumder ,  Chukwudi Azubuike Okoro ,  Ah-Young Park ,  Scott Christopher Pollard ,  Rajesh Vaddi

IPC: C25D3/38 ,  C03C3/06 ,  C03C15/00 ,  C03C17/06 ,  C03C17/10 ,  C03C23/00 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/15 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/38 ,  C03C3/076 ,  C25D7/12 ,  H01L23/00 ,  H01L23/492 ,  H05K3/00 ,  H05K3/42

CPC classification number: H01L23/49827 ,  C03C3/06 ,  C03C15/00 ,  C03C17/06 ,  C03C17/10 ,  C03C23/0025 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H01L21/76877 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49838 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/388 ,  C03C3/076 ,  C03C2218/115 ,  C25D3/38 ,  C25D7/123 ,  H01L21/486 ,  H01L23/4924 ,  H01L23/49866 ,  H01L23/564 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/0055 ,  H05K3/423 ,  H05K3/425 ,  H05K3/428 ,  H05K2201/068 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/0989 ,  H05K2201/10378 ,  H05K2203/1194 ,  H05K2203/1361 ,  H05K2203/143 ,  H05K2203/1438 ,  H05K2203/162 ,  Y10T428/24273 ,  Y10T428/24479 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

公开(公告)号：US11937373B2

公开(公告)日：2024-03-19

申请号：US17689611

申请日：2022-03-08

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Paul Danna ,  Chi Kim Sides ,  Wayne Vuong ,  Michael Chan

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/09263 ,  H05K2201/09609

Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.

公开(公告)号：US20230411832A1

公开(公告)日：2023-12-21

申请号：US18459597

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Min CHO ,  Chan-Gi PARK ,  Yeon-Sang YUN ,  Tae-Wook HAM ,  Hei-Seong KWAK ,  Byoung-Il SON ,  Sung-Chul PARK

IPC: H01Q1/24 ,  H01Q5/35 ,  H05K1/02 ,  H01Q21/28 ,  H01Q1/38 ,  H01R12/79 ,  H01R13/66 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K7/14

CPC classification number: H01Q1/243 ,  H01Q5/35 ,  H05K1/0218 ,  H01Q21/28 ,  H01Q1/38 ,  H01R12/79 ,  H01R13/6691 ,  H05K1/0243 ,  H05K1/028 ,  H05K1/115 ,  H05K1/142 ,  H05K1/148 ,  H05K1/18 ,  H05K7/1427 ,  H05K2201/0999 ,  H05K2201/09609 ,  H05K2201/10098

Abstract: Disclosed is a portable communication device including a housing; a first PCB; a wireless communication circuitry disposed on the first PCB; and a second PCB having a plurality of layers including a first PCB portion; a second PCB portion extended from the first PCB portion and more flexible than the first PCB portion; a third PCB portion extended from the second PCB portion and less flexible than the second PCB portion; a fourth PCB portion extended from the third PCB portion and more flexible than the third PCB portion; and a plurality of lines formed at a same layer of the plurality of layers as extended from the second PCB portion through the third PCB portion to the fourth PCB portion, the plurality of lines including a first ground line and a second ground line, and a first signal line between the first and second ground lines.

公开(公告)号：US11749880B2

公开(公告)日：2023-09-05

申请号：US18090214

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Min Cho ,  Chan-Gi Park ,  Yeon-Sang Yun ,  Tae-Wook Ham ,  Hei-Seong Kwak ,  Byoung-Il Son ,  Sung-Chul Park

IPC: H01Q1/24 ,  H01Q5/35 ,  H05K1/02 ,  H01Q21/28 ,  H01Q1/38 ,  H01R12/79 ,  H01R13/66 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K7/14

CPC classification number: H01Q1/243 ,  H01Q1/38 ,  H01Q5/35 ,  H01Q21/28 ,  H01R12/79 ,  H01R13/6691 ,  H05K1/028 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/115 ,  H05K1/142 ,  H05K1/148 ,  H05K1/18 ,  H05K7/1427 ,  H05K2201/0999 ,  H05K2201/09609 ,  H05K2201/10098

Abstract: Disclosed is a portable communication device including a housing, a first printed circuit board (PCB) disposed in the housing, a wireless communication circuit mounted on the first PCB, and a second PCB including a connection part connected with the first PCB, a first PCB portion extended from the connection part and having greater flexibility than the connection part, a second PCB portion extended from the first PCB portion and having less flexibility than the first PCB portion, a third PCB portion extended from the second PCB portion and having greater flexibility than the second PCB portion, a fourth PCB portion extended from the third PCB portion and having less flexibility than the first PCB portion, a signal line extended to the connection part along the first, second, third, and fourth PCB portions, and vias arranged in at least a partial area of the second PCB portion or the fourth PCB portion, wherein a portion of the signal line is located between some of the vias.

公开(公告)号：US20180376581A1

公开(公告)日：2018-12-27

申请号：US16009397

申请日：2018-06-15

Applicant: Daisuke FUJIOKA

Inventor： Daisuke FUJIOKA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0228 ,  H01R12/716 ,  H01R12/722 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/09609 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: A circuit board has a base layer composed of multiple layers, and the base layer includes a connector to which a wire harness carrying a signal is coupled, the connector being fixed to a slot for mounting, and a plurality of GND plane patterns arranged in a plurality of layers and electrically coupled to each other through at least one via. Each one of the multiple layers of the base layer includes one of the plurality of GND plane patterns. In and around an area in which the connector is disposed, each one of the plurality of GND plane patterns is provided for a respective one of the multiple layers. The at least one via is arranged around the area in which the connector is disposed. The base layer includes a frame, and at least one via is arranged in the frame.

公开(公告)号：US20180277471A1

公开(公告)日：2018-09-27

申请号：US15994006

申请日：2018-05-31

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/00 ,  H01L23/48 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

公开(公告)号：US20180184514A1

公开(公告)日：2018-06-28

申请号：US15807648

申请日：2017-11-09

Applicant: FUJITSU LIMITED

Inventor： Tetsuro Yamada ,  AKIKO MATSUI ,  Mitsuhiko Sugane ,  Takahide Mukoyama ,  YOSHIYUKI HIROSHIMA ,  Kohei Choraku

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00

CPC classification number: H05K1/0213 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H05K1/0265 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K2201/09463 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.

公开(公告)号：US09980407B2

公开(公告)日：2018-05-22

申请号：US15507364

申请日：2015-09-17

Applicant: DENSO CORPORATION

Inventor： Takashi Yoshimizu ,  Yuuki Sanada

IPC: H05K7/20 ,  H05K7/14 ,  H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H05K1/18 ,  H01L23/10 ,  H01G2/06 ,  H01G2/10 ,  H05K1/11 ,  H01L23/367 ,  H01G2/08 ,  H05K1/02 ,  H01L23/473

CPC classification number: H05K7/1427 ,  H01G2/065 ,  H01G2/08 ,  H01G2/103 ,  H01L23/053 ,  H01L23/10 ,  H01L23/12 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49844 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/115 ,  H05K1/117 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10303 ,  H05K2201/10371 ,  H05K2201/1056 ,  H05K2201/1059 ,  H05K2203/1327 ,  H01L2924/00

Abstract: An electronic device includes a circuit board with an insulating substrate, a wiring at the substrate, an electronic component mounted at the substrate and electrically connected to the wiring, at least one through hole through the substrate from one surface to an opposite surface of the one surface of the substrate, and a conductive member arranged at a surface of the through hole and electrically connected to the wiring; and further includes: a sealing resin; and a cap including an annular connection with a part connected to the substrate and a recess recessed from the annular connection. Furthermore, in the cap, at least a part of the connection is connected to the substrate, the cap being sealed integrally with the electronic component by the sealing resin while arranging a space communicating with the through hole; and a terminal is inserted into the through hole and electrically connected to the wiring.

公开(公告)号：US09844135B2

公开(公告)日：2017-12-12

申请号：US14480430

申请日：2014-09-08

Applicant: Cisco Technology, Inc.

Inventor： Feng Wu ,  Yongchao Ji ,  Yang Tang ,  Stephen Scearce ,  Shunjia Liu ,  Shaochun Tang

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/3415 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10674

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

公开(公告)号：US09729188B2

公开(公告)日：2017-08-08

申请号：US15276179

申请日：2016-09-26

Applicant: Electrochem Solutions, Inc.

Inventor： Gregory G. Decker ,  Brian R. Peterson ,  Eric Jankins

IPC: H04B1/40 ,  H02J50/10 ,  H02M7/155 ,  H05K1/02 ,  H05K1/11

CPC classification number: H04B1/40 ,  H02J7/0029 ,  H02J7/025 ,  H02J50/10 ,  H02J50/12 ,  H02J50/80 ,  H02J2007/0037 ,  H02J2007/004 ,  H02M7/155 ,  H04B5/0031 ,  H04B5/0037 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/0707 ,  H05K2201/09609

Abstract: A system for harnessing and conditioning wirelessly transmitted electrical energy by near field magnetic induction configured with various magnetic field shielding embodiments is disclosed. The shielding embodiments are designed to minimize electromagnetic interference and induced electrical current. The system comprises an electrical energy capture circuit and an RF communication circuit. The electrical energy capture circuit conditions and modifies the wirelessly received electrical energy. The RF communication circuit enables the system to wirelessly communicate with its sub-circuits and other energy capture systems. The system comprises a tunable band stop filter that is electrically connected to the RF communication sub-circuit. In addition, the RF communication sub-circuit is configured with opposing electrically conductive plates that isolate and shield the circuit from an oscillating magnetic field.