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公开(公告)号：US4831521A
公开(公告)日：1989-05-16
申请号：US550693
申请日：1983-11-10
申请人： David B. Rutherford
发明人： David B. Rutherford
CPC分类号： G06F11/10 , G06F11/076 , G06F11/0763 , G06F11/08 , G06F7/724
摘要： A method and apparatus for effecting vital functions notwithstanding the fact that non-vital hardware is employed. A vital processor is implemented using non-vital hardware in the form of a digital computer which may for example be a microprocessor. The vital processor accepts binary input values and, based on a series of logical expressions relating output values to input values, determines the appropriate output values. Rather than employing a single bit to represent the condition of a particular input or output, unique multibit binary values or names are used. Each input or output has assigned to it at least two unique multibit values, each satisfying the code rules of a different code. Thus rather than representing a closed contact as a single 1 bit, and an open contact as a single 0 bit, the closed contact is represented by a unique multibit name which satisfies the code rules of a first code. At any point in the processing the value representing the contact can be checked to see if it satisfies the code rules, and if it does not a potential error is detected and handled. Although it is highly unlikely that a hardware failure would result in generating one of the few multibit names satisfying the code rule, that occurrence is not unlikely enough to be considered vital. Before actually controlling output devices in accordance with the processing, further tests are implemented which ensure that the multibit value computed for a particular output not only satisfies the predetermined code rule which is required, but is also correct bit for bit. Logic equations describing the relationship between output and input are actually computed using the multibit values as opposed to single bit values.
摘要翻译： 尽管采用非重要硬件的事实，仍然用于实现重要功能的方法和装置。 使用数字计算机形式的非重要硬件实现重要的处理器，数字计算机可以是例如微处理器。 重要的处理器接受二进制输入值，并且基于将输出值与输入值相关联的一系列逻辑表达式，确定适当的输出值。 不使用单个位来表示特定输入或输出的条件，而是使用唯一的多位二进制值或名称。 每个输入或输出分配给至少两个唯一的多位值，每个值都满足不同代码的代码规则。 因此，不是将单个1位的闭合触点和作为单个0位的开放触点表示，所以闭合触点由满足第一代码的代码规则的唯一多位名称表示。 在处理的任何时刻，可以检查表示联系人的值，以查看它是否满足代码规则，并且如果不检测和处理潜在的错误。 尽管硬件故障极不可能导致产生满足代码规则的少数几个名称之一，但这种发生并不太可能被认为是至关重要的。 在根据处理实际控制输出设备之前，实施进一步的测试，确保为特定输出计算的多位值不仅满足所需的预定代码规则，而且还是位的正确位。 描述输出和输入之间的关系的逻辑方程实际上是使用多位值而不是单个位值来计算的。
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公开(公告)号：US4956779A
公开(公告)日：1990-09-11
申请号：US267218
申请日：1988-11-22
申请人： David B. Rutherford
发明人： David B. Rutherford
CPC分类号： B61L3/008 , B60L15/20 , B60L2200/26 , Y02T10/645 , Y02T10/7275
摘要： The functions to be performed by a digital overspeed controller are implemented by application of two concepts, namely "diverse channels" and "even/odd systems cycles"; in accordance with the first concept, two channels are maintained throughout the overspeed controller, beginning with two independent tachometer inputs; all of the functions involve operations to be performed in each of the two channels separately. The numerical results for each of the channels are different and the numerical difference between the two channels is used to prove the integrity of the functions described. The second concept of "even/odd system cycles" involves a "system cycle time", denoted T.sub.CYC, that is nominally 100 milliseconds. All of the functions of the controller are performed each system cycle. In order to be able to vitally distinguish data results between adjacent cycles, the cycles are denoted EVEN and ODD, and the results of each of the operations produce different numerical values on even and odd cycles.
摘要翻译： 由数字超速控制器执行的功能是通过应用“不同通道”和“偶数/奇数系统周期”两个概念实现的。 根据第一个概念，在整个超速控制器中保持两个通道，从两个独立的转速计输入开始; 所有功能涉及在两个通道中的每个通道中分别执行的操作。 每个通道的数值结果不同，两个通道之间的数值差异用于证明所述功能的完整性。 “偶数/奇数系统周期”的第二个概念涉及名义上为100毫秒的表示为TCYC的“系统周期时间”。 每个系统周期执行控制器的所有功能。 为了能够区分相邻周期之间的数据结果，这些周期表示为EVEN和ODD，并且每个运算的结果在偶数和奇数周期上产生不同的数值。
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公开(公告)号：US4196412A
公开(公告)日：1980-04-01
申请号：US869740
申请日：1978-01-16
IPC分类号： B61L29/24 , G08G1/0967 , G08G1/02 , G08B23/00
CPC分类号： G08G1/096716 , B61L29/246 , G08G1/096758 , G08G1/096783
摘要： Apparatus for insuring a vehicle operator's attentiveness at potentially dangerous locations along a path of travel. A signalling device is provided in advance of a potentially dangerous location, in the direction of travel of the vehicle. A vehicle carried signal responsive device responds to the signalling device when within the effective zone of the signalling device. The vehicle includes warning apparatus, for example, an alarm and a buzzer. The vehicle also includes an operator actuatable push button and a speed sensing apparatus. A control device responds to the push button and to the vehicle carried signal responsive device to operate either the buzzer or the alarm. If the operator evidences his alertness to the potentially dangerous location by actuating the push button prior to reaching the signalling device (within some constraint), the control apparatus merely sounds the buzzer when the signalling device is detected and resets itself. On the other hand, if the operator fails to actuate the push button in advance of detection of the signalling device, or, if his actuation is too far in advance of detection, then the alarm is energized and will remain energized until the vehicle is brought to a stop, or a low speed, at which point, push button actuation can cancel the alarm.
摘要翻译： 用于确保车辆操作员在沿着行进路线的潜在危险位置的注意力的装置。 在潜在的危险位置之前，在车辆的行进方向上提供信号装置。 当信号装置的有效区域内时，车载信号响应装置响应信令装置。 车辆包括警报装置，例如报警器和蜂鸣器。 该车辆还包括操作者致动按钮和速度检测装置。 控制装置响应于按钮和车载信号响应装置来操作蜂鸣器或报警器。 如果操作者通过在到达信令装置之前（在一定的约束条件下）启动按钮来证明其对潜在危险位置的警觉性，则当检测到信令装置并且自动重置时，控制装置仅发出蜂鸣器。 另一方面，如果操作者在检测到信号装置之前未能按下按钮，或者如果其启动在检测之前太远，则报警器被通电并且将保持通电直到车辆被带入 停止或低速，此时按钮启动可以取消报警。
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公开(公告)号：US5048064A
公开(公告)日：1991-09-10
申请号：US267214
申请日：1988-11-04
申请人： David B. Rutherford
发明人： David B. Rutherford
CPC分类号： G06F11/076
摘要： A vital microcompressor-based rate decoder for use in a vital processing system in on-board main line railroad and rapid transit automatic train protection systems; the design is such that a method is incorporated for tolerating specific kinds of signal disruption and in such a way that the probability of a wrongside failure has a calculable upper bound. A pickup coil transmits external or wayside signals to an arrangement which involves two channels and which provides period and duty cycle measurement of the pulses resulting from demodulation of the external signals. A counter is employed in each of the channels and a tolerance accumulation rate decoding device is included, the maximum amount of tolerance accumulated, and the minimum time required to accumulate it, being functions of the rate code selected.
摘要翻译： 一种重要的基于微压缩器的速率解码器，用于车载主线铁路和快速过境自动列车保护系统中的重要处理系统; 这种设计是为了容忍特定种类的信号中断并且以这样的方式引入了一种方法，使得错误的失败的概率具有可计算的上限。 拾取线圈将外部或路边信号传输到涉及两个通道的布置，并且其提供由外部信号的解调产生的脉冲的周期和占空比测量。 在每个通道中使用计数器，并且包括公差累积速率解码装置，累积的最大容差量和累积所需的最小时间，作为选择的速率代码的函数。
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5.发明授权Vital processing system including a vital power controller with forgiveness feature 失效重要的处理系统包括具有宽恕功能的重要功率控制器
公开(公告)号：US4949273A
公开(公告)日：1990-08-14
申请号：US267070
申请日：1988-11-04
CPC分类号： G06F11/0796 , G06F11/00 , G06F11/0757 , G06F11/0763
摘要： The present device, a vital power controller with forgiveness, is a subsystem of a larger vital processing system, the function of the subsystem being to verify the proper operation of the larger system and to provide power to the system outputs only when the larger system functions correctly; the larger system periodically delivers checkword sets to the vital power controller (VPC); the checkwords verify the correct operation of the larger system, a valid checkword set enabling the VPC to generate vital power for a limited time; the forgiveness feature allows the VPC to tolerate an occasional bad checkword set and yet continue to provide vital power if the rate at which bad checkword sets is encountered is below a specified rate, thereby providing improved performance in the presence of noise which tends to produce occasional bad checkwords and which would otherwise cause loss of vital power.
摘要翻译： 本设备是具有宽恕性的重要功率控制器，是较大的重要处理系统的子系统，子系统的功能是验证较大系统的正常运行，并且仅在较大系统功能时才向系统输出供电 正确的 较大的系统周期性地向重要功率控制器（VPC）提供校验字集合; 核对单词验证较大系统的正确操作，一个有效的检查词，使VPC能够在有限的时间内产生生命力; 宽恕功能允许VPC容忍偶尔的错误勾号，并且如果遇到错误的单词集的速率低于规定的速率，并且继续提供重要的功率，从而在存在噪声的情况下提供改进的性能，这倾向于偶尔产生 不好的支票，否则会导致生命力的损失。
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公开(公告)号：US4168526A
公开(公告)日：1979-09-18
申请号：US882688
申请日：1978-03-02
摘要： A microprocessor based vital delay circuit is provided which is arranged to emit an output no less than a predetermined time after an input stimulus. The predetermined time, which corresponds to the delay, is controlled by selecting the relationship between two quantities. A digital processor performs a series of computations on the two quantities, each computation is arranged to take unit time and by selecting the proper relationship between the two quantities, the total series of computations takes a predetermined amount of time. Before the output is allowed to occur, several checks are performed to insure that no hardware or software failures have erroneously generated the result. One novel checking technique insures that the clock frequency has not changed, and this technique is applicable to a wide variety of devices in which digital techniques are employed.
摘要翻译： 提供了一种基于微处理器的重要延迟电路，其被布置成在输入刺激之后发出不少于预定时间的输出。 通过选择两个量之间的关系来控制对应于延迟的预定时间。 数字处理器对两个量进行一系列计算，每个计算被设置为花费单位时间，并且通过选择两个量之间的适当关系，总计一系列计算需要预定的时间量。 在允许输出发生之前，会执行几次检查，以确保没有硬件或软件故障错误地生成结果。 一种新颖的检查技术确保时钟频率没有改变，并且该技术适用于采用数字技术的各种设备。
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