公开(公告)号：US20190095350A1

公开(公告)日：2019-03-28

申请号：US15714217

申请日：2017-09-25

申请人： David M. Durham ,  Siddhartha Chhabra ,  Amy L. Santoni ,  Gilbert Neiger ,  Barry E. Huntley ,  Hormuzd M. Khosravi ,  Baiju V. Patel ,  Ravi L. Sahita ,  Gideon Gerzon ,  Ido Ouziel ,  Ioannis T. Schoinas ,  Rajesh M. Sankaran

发明人： David M. Durham ,  Siddhartha Chhabra ,  Amy L. Santoni ,  Gilbert Neiger ,  Barry E. Huntley ,  Hormuzd M. Khosravi ,  Baiju V. Patel ,  Ravi L. Sahita ,  Gideon Gerzon ,  Ido Ouziel ,  Ioannis T. Schoinas ,  Rajesh M. Sankaran

IPC分类号： G06F12/14 ,  G06F21/60 ,  G06F21/82 ,  G06F3/06

摘要： In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read request having a memory address from a first agent, obtain a key identifier for a key of the first agent from the data line, obtain the key using the key identifier, decrypt the at least encrypted portion of the data line using the key and send decrypted data of the at least encrypted portion of the data line to the first agent. Other embodiments are described and claimed.

公开(公告)号：US20150058510A1

公开(公告)日：2015-02-26

申请号：US14538941

申请日：2014-11-12

申请人： Gilbert Neiger ,  Rajesh M. Sankaran ,  Gideon Gerzon ,  Richard A. Uhlig ,  Sergiu D. Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

发明人： Gilbert Neiger ,  Rajesh M. Sankaran ,  Gideon Gerzon ,  Richard A. Uhlig ,  Sergiu D. Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

IPC分类号： G06F13/26 ,  G06F9/455

CPC分类号： G06F13/26 ,  G06F9/30076 ,  G06F9/45541 ,  G06F9/45558 ,  G06F13/24 ,  G06F2009/45579 ,  G06F2213/0058

摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

摘要翻译： 公开了用于虚拟化中断优先级和传送的处理器，方法和系统的实施例。 在一个实施例中，处理器包括指令硬件和执行硬件。 指令硬件是接收多个指令，包括将处理器从根模式传送到非根模式的第一指令，用于在虚拟机中执行客户软件，其中处理器将根据该模式返回到根模式 检测多个虚拟机退出事件中的任何一个。 执行硬件是执行第一指令，执行第一指令以包括确定第一虚拟处理器优先级值并将第一虚拟处理器优先级值存储在处理器优先级字段的虚拟副本中，其中虚拟副本 处理器优先级字段是对应于与中断控制器相关联的物理资源的虚拟资源。

公开(公告)号：US08910158B2

公开(公告)日：2014-12-09

申请号：US13325714

申请日：2011-12-14

申请人： Gilbert Neiger ,  Rajesh M. Sankaran ,  Gideon Gerzon ,  Richard A. Uhlig ,  Sergiu D. Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

发明人： Gilbert Neiger ,  Rajesh M. Sankaran ,  Gideon Gerzon ,  Richard A. Uhlig ,  Sergiu D. Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

IPC分类号： G06F9/455

CPC分类号： G06F13/26 ,  G06F9/30076 ,  G06F9/45541 ,  G06F9/45558 ,  G06F13/24 ,  G06F2009/45579 ,  G06F2213/0058

摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

摘要翻译： 公开了用于虚拟化中断优先级和传送的处理器，方法和系统的实施例。 在一个实施例中，处理器包括指令硬件和执行硬件。 指令硬件是接收多个指令，包括将处理器从根模式传送到非根模式的第一指令，用于在虚拟机中执行客户软件，其中处理器将根据该模式返回到根模式 检测多个虚拟机退出事件中的任何一个。 执行硬件是执行第一指令，执行第一指令以包括确定第一虚拟处理器优先级值并将第一虚拟处理器优先级值存储在处理器优先级字段的虚拟副本中，其中虚拟副本 处理器优先级字段是对应于与中断控制器相关联的物理资源的虚拟资源。

公开(公告)号：US20130159579A1

公开(公告)日：2013-06-20

申请号：US13325714

申请日：2011-12-14

申请人： Gilbert Neiger ,  Rajesh M. Sankaran ,  Gideon Gerzon ,  Richard A. Uhlig ,  Sergiu D. Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

发明人： Gilbert Neiger ,  Rajesh M. Sankaran ,  Gideon Gerzon ,  Richard A. Uhlig ,  Sergiu D. Ghetie ,  Michael Neve de Mevergnies ,  Adil Karrar

IPC分类号： G06F13/26

CPC分类号： G06F13/26 ,  G06F9/30076 ,  G06F9/45541 ,  G06F9/45558 ,  G06F13/24 ,  G06F2009/45579 ,  G06F2213/0058

摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

公开(公告)号：US20170024584A1

公开(公告)日：2017-01-26

申请号：US14979002

申请日：2015-12-22

申请人： Siddhartha Chhabra ,  Gideon Gerzon ,  Reshma Lal ,  Bin Xing ,  Pradeep M. Pappachan ,  Steven B. McGowan

发明人： Siddhartha Chhabra ,  Gideon Gerzon ,  Reshma Lal ,  Bin Xing ,  Pradeep M. Pappachan ,  Steven B. McGowan

IPC分类号： G06F21/72 ,  H04L9/32 ,  H04L9/08

CPC分类号： G06F21/72 ,  G06F21/57 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/3242

摘要： Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The computing device establishes, an invoking secure enclave using secure enclave support of a processor. The invoking enclave configures channel programming information, including a channel key, and invokes a processor instruction with the channel programming information as a parameter. The processor generates wrapped programming information including an encrypted channel key and a message authentication code. The encrypted channel key is protected with a key known only to the processor. The invoking enclave provides the wrapped programming information to untrusted software, which invokes a processor instruction with the wrapped programming information as a parameter. The processor unwraps and verifies the wrapped programming information and then programs the cryptographic engine. The processor generates an authenticated response that may be verified by the invoking enclave. Other embodiments are described and claimed.

摘要翻译： 用于加密引擎的安全编程的技术包括具有密码引擎和一个或多个I / O控制器的计算设备。 计算设备使用处理器的安全飞地支持来建立调用安全飞地。 调用飞地配置信道编程信息，包括信道密钥，并且以通道编程信息为参数来调用处理器指令。 处理器产生包括加密的信道密钥和消息认证码的包装节目信息。 加密的通道密钥由仅对处理器已知的密钥进行保护。 调用的包层将包装的编程信息提供给不受信任的软件，该软件以包装的编程信息作为参数调用处理器指令。 处理器解封装并验证封装的编程信息，然后对加密引擎进行编程。 处理器生成可以通过调用飞地验证的认证响应。 描述和要求保护其他实施例。

公开(公告)号：US08230203B2

公开(公告)日：2012-07-24

申请号：US11694344

申请日：2007-03-30

申请人： Gilbert Neiger ,  Randolph L. Campbell ,  James B. Crossland ,  Gideon Gerzon ,  Leena K. Puthiyedath ,  Stephen A. Fischer ,  Steven M. Bennett ,  Andrew V. Anderson

发明人： Gilbert Neiger ,  Randolph L. Campbell ,  James B. Crossland ,  Gideon Gerzon ,  Leena K. Puthiyedath ,  Stephen A. Fischer ,  Steven M. Bennett ,  Andrew V. Anderson

IPC分类号： G06F9/00 ,  G06F9/455

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.

摘要翻译： 公开了在虚拟机环境中检测自旋回路的装置，方法和系统的实施例。 在一个实施例中，装置包括检测逻辑和虚拟逻辑。 检测逻辑是检测访客是否正在执行自旋循环。 响应于检测到客户正在执行自旋回路的检测逻辑，虚拟化逻辑是将设备的控制从客户转移到主机。

公开(公告)号：US08566492B2

公开(公告)日：2013-10-22

申请号：US12650581

申请日：2009-12-31

申请人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

发明人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

公开(公告)号：US20140365696A1

公开(公告)日：2014-12-11

申请号：US14467604

申请日：2014-08-25

申请人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

发明人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic. and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

摘要翻译： 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，一种装置包括查找逻辑。 和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。

公开(公告)号：US20130232288A1

公开(公告)日：2013-09-05

申请号：US13837730

申请日：2013-03-15

申请人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

发明人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

摘要翻译： 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，装置包括查找逻辑和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。

公开(公告)号：US20110161541A1

公开(公告)日：2011-06-30

申请号：US12650581

申请日：2009-12-31

申请人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

发明人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

摘要翻译： 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，装置包括查找逻辑和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。