公开(公告)号：US4731589A

公开(公告)日：1988-03-15

申请号：US889209

申请日：1986-07-25

申请人： Donald R. Preslar

发明人： Donald R. Preslar

IPC分类号： H03F3/30 ,  H03F3/45 ,  H03F3/26

CPC分类号： H03F3/3096 ,  H03F3/45071

摘要： Level shifter circuitry, as for an operational amplifier, imposes no current load on the preceding amplifier stage associated with its level shifter function. A common-collector-amplifier first transistor has base and emitter connections to the input and output terminals of the level shifter. A second transistor of similar conductivity type and common-collector forward current gain has its base electrode connected through a first current mirror amplifier to the input terminal of the level shifter and has its emitter electrode connected through a second current mirror amplifier to the output terminal of the level shifter. The first and second current mirror amplifiers have similar current gains. The first current mirror amplifier may also be incorporated in apparatus for supplying constant current loading to the preceding amplifier stage, to this end having a source of constant current connected to its input connection.

摘要翻译： 对于运算放大器，电平移位器电路在与其电平移位器功能相关联的前一放大器级上不施加电流负载。 公共集电极放大器第一晶体管具有与电平移位器的输入和输出端子的基极和发射极连接。 类似导电类型和共集电极正向电流增益的第二晶体管的基极通过第一电流镜放大器连接到电平移位器的输入端，并且其发射极通过第二电流镜放大器连接到输出端 电平转换器。 第一和第二电流镜放大器具有类似的电流增益。 第一电流镜放大器也可以并入用于向前一放大器级提供恒定电流负载的装置中，为此，其具有连接到其输入连接的恒定电流源。

公开(公告)号：US4442409A

公开(公告)日：1984-04-10

申请号：US352179

申请日：1982-02-25

申请人： Donald R. Preslar

发明人： Donald R. Preslar

IPC分类号： H03F3/30

CPC分类号： H03F3/3096

摘要： A push-pull amplifier having like conductivity output transistors is driven by a phase-splitter transistor amplifier. The collector load of the phase-splitter includes a diode bridge for establishing the amplifier idling current. One arm of the bridge incorporates the pull-up output transistor base-emitter junction-the current conducted therein being accurately determined by bridge parameters.

摘要翻译： 具有类似导电输出晶体管的推挽放大器由分相器晶体管放大器驱动。 分相器的集电极负载包括用于建立放大器空转电流的二极管桥。 桥的一个臂结合了上拉输出晶体管基极 - 发射极结，其中传导的电流由桥参数精确地确定。

公开(公告)号：US06919758B1

公开(公告)日：2005-07-19

申请号：US10721624

申请日：2003-11-25

申请人： Donald R. Preslar ,  Thomas J. Hayes

发明人： Donald R. Preslar ,  Thomas J. Hayes

IPC分类号： G05F1/10 ,  G05F1/575

CPC分类号： G05F1/575

摘要： A controller for regulating a FET to operate as a pass device including input, output and gate nodes coupled to a current path input, a current path output and the gate of the FET, respectively, a controlled low current device, and an oscillating high gain regulation amplifier. The voltage source provides a regulation voltage level relative to the input node. The low current device is coupled to the gate node and has a control input. The amplifier has a first input coupled to the output node, a second input coupled to the voltage source, and an output coupled to the control input of the controlled low current device to regulate the FET. The amplifier oscillates while regulating a voltage between the input and output nodes to the regulation voltage level. The controlled low current device presents a high impedance to the gate node to prevent oscillations from disturbing regulation.

摘要翻译： 一种用于调节FET作为通过装置的控制器，其包括分别耦合到电流路径输入，电流路径输出和FET的栅极的输入，输出和栅极节点，受控低电流装置和振荡高增益 调节放大器。 电压源提供相对于输入节点的调节电压电平。 低电流器件耦合到栅极节点并具有控制输入。 放大器具有耦合到输出节点的第一输入端，耦合到电压源的第二输入端和耦合到受控低电流器件的控制输入的输出端以调节FET。 放大器在将输入和输出节点之间的电压调节到调节电压电平的同时振荡。 受控的低电流器件对栅极节点呈现高阻抗，以防止振荡干扰调节。

公开(公告)号：US6069502A

公开(公告)日：2000-05-30

申请号：US55528

申请日：1998-04-06

申请人： Donald R. Preslar ,  Salomon Vulih

发明人： Donald R. Preslar ,  Salomon Vulih

IPC分类号： G11C27/02

CPC分类号： G11C27/026

摘要： An integrated sample-and-hold S/H circuit includes a subthreshold conduction current compensation circuit for reducing undesired effects of subthreshold conduction current in a first field-effect transistor (FET) during the holding time. More particularly, the S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and the first FET. The first FET has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal. The control terminal is responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time and for disconnecting the input signal from the sampling capacitor during a holding time. The first FET preferably further includes a body which unfortunately creates a parasitic diode connected to the sampling capacitor. A unity gain buffer amplifier may be connected to the body of the first FET during the holding time for applying a holding voltage from the sampling capacitor to the body to thereby reduce undesired effects from the parasitic diode. The subthreshold current conduction compensation circuit causes a voltage at the first conduction terminal of the first FET to be substantially equal to a voltage at the second conduction terminal of the first FET during the holding time. This may be accomplished by coupling the holding voltage from the output of the buffer amplifier to the node between two series connected FETs.

摘要翻译： 集成的采样和保持S / H电路包括用于在保持时间期间减少第一场效应晶体管（FET）中的亚阈值导通电流的不期望的影响的亚阈值传导电流补偿电路。 更具体地，S / H电路可以包括衬底，形成在衬底上的采样电容器和第一FET。 第一FET具有用于接收输入信号的第一导通端子，连接到采样电容器的第二导通端子和控制端子。 控制端子响应于在采样时间期间将输入信号连接到采样电容器的控制信号，以及在保持时间期间从采样电容器断开输入信号。 第一FET优选地还包括不幸地产生连接到采样电容器的寄生二极管的主体。 在保持时间期间，可以将单位增益缓冲放大器连接到第一FET的主体，以将来自采样电容器的保持电压施加到主体，从而减少来自寄生二极管的不期望的影响。 亚阈值电流导通补偿电路使得第一FET的第一导通端子处的电压在保持时间期间基本上等于第一FET的第二导通端子处的电压。 这可以通过将保持电压从缓冲放大器的输出耦合到两个串联连接的FET之间的节点来实现。

公开(公告)号：US6002277A

公开(公告)日：1999-12-14

申请号：US55561

申请日：1998-04-06

申请人： Salomon Vulih ,  Donald R. Preslar ,  Thomas A. Jochum

发明人： Salomon Vulih ,  Donald R. Preslar ,  Thomas A. Jochum

IPC分类号： G11C27/02 ,  H03K17/00

CPC分类号： G11C27/026

摘要： An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET. The holding voltage overcomes the voltage droop as would otherwise be caused by the parasitic diode. The switches may also connect the body of the first FET to a supply voltage during the sampling time. In addition, the buffer amplifier may have a substantially unity gain.

摘要翻译： 集成S / H电路包括形成在具有采样电容器的衬底上的第一场效应晶体管（FET）和具有连接到采样电容器的输入端的缓冲放大器和可连接到第一FET的本体的输出。 因此，缓冲放大器减少了由主体和采样电容器形成的寄生二极管的不期望的影响。 更具体地，第一FET优选地具有用于接收输入信号的第一导通端子，连接到采样电容器的第二导通端子和响应于在采样时间期间将输入信号连接到采样电容器的控制信号的控制端子， 并且用于在保持时间期间从采样电容器断开输入信号。 电路可以包括用于在保持时间期间将第一FET的主体连接到缓冲放大器的输出的一个或多个开关，从而将采样电容器的保持电压施加到第一FET的主体。 保持电压克服了否则将由寄生二极管引起的电压下降。 开关还可以在采样时间期间将第一FET的主体连接到电源电压。 此外，缓冲放大器可以具有基本上单位增益。

公开(公告)号：US4322643A

公开(公告)日：1982-03-30

申请号：US144053

申请日：1980-04-28

申请人： Donald R. Preslar

发明人： Donald R. Preslar

IPC分类号： H03K7/08 ,  H03D13/00 ,  H03K5/26 ,  H03L7/089 ,  H03L7/183

CPC分类号： H03D13/004 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/183

摘要： A digital phase comparator for essentially eliminating the dead zone in the phase correction means of a phase locked loop. The digital phase comparator is arranged to provide respective up and down output pulses to operate respective charge pumps. The up and down output pulses at all times are greater than a predetermined time duration no matter how small the phase difference between comparator input signals. A delay means is provided in the phase comparator logic, which delay means substantially determines such predetermined time duration. The minimum pulse duration of the up and down signals is selected to be at least of a duration sufficient to operate its respective charge pump, thereby overcoming the finite turn on time of the respective charge pump, no matter how small the phase error.

摘要翻译： 数字相位比较器，用于基本消除锁相环相位校正装置中的死区。 数字相位比较器布置成提供各自的上下输出脉冲以操作相应的电荷泵。 无论比较器输入信号之间的相位差有多小，所有时间的上下输出脉冲均大于预定的持续时间。 在相位比较器逻辑中提供延迟装置，该延迟装置基本上确定这样的预定持续时间。 上升和下降信号的最小脉冲持续时间被选择为至少足以操作其相应电荷泵的持续时间，从而克服相应电荷泵的有限导通时间，而不管相位误差有多小。

公开(公告)号：US07031175B2

公开(公告)日：2006-04-18

申请号：US10797437

申请日：2004-03-10

申请人： Noel B. Dequina ,  Donald R. Preslar ,  Paul K. Sferrazza

发明人： Noel B. Dequina ,  Donald R. Preslar ,  Paul K. Sferrazza

IPC分类号： H02M7/217

CPC分类号： H02M1/088 ,  H02M1/38 ,  H02M3/1588 ,  H03K17/0822 ,  H03K17/6871 ,  Y02B70/1466

摘要： A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.

摘要翻译： 一种用于包括采样电路和比较器的同步整流FET驱动器的体二极管比较器电路。 FET驱动器具有耦合在一对上开关FET和下开关FET之间的相位节点，并且响应于具有用于每个周期的第一和第二相的PWM信号。 采样电路在PWM信号的第一阶段期间对相位节点的初始电压进行采样，并且在PWM信号的第二阶段期间提供指示相位节点的初始相位电压的和电压。 比较器将和电压与预定参考电压进行比较，并在PWM信号的第二阶段期间提供指示下FET的激活状态的输出。 当比较器指示下部FET关闭时，FET驱动器接通上部FET。

公开(公告)号：US5608259A

公开(公告)日：1997-03-04

申请号：US204718

申请日：1994-03-02

申请人： Thomas R. DeShazo ,  Raymond L. Giordano ,  Donald R. Preslar

发明人： Thomas R. DeShazo ,  Raymond L. Giordano ,  Donald R. Preslar

IPC分类号： H01L29/8605 ,  H01L29/00

CPC分类号： H01L29/8605

摘要： An IC is constructed with deep layers preventing current flow due to parasitic transistors formed within the IC. Reverse current in case of voltage source polarity reversal is prevented by means of the reverse bias diodes formed by the addition of a P+ ring, and N+ well, for the embodiment disclosed.

摘要翻译： IC由深层构成，防止由IC内形成的寄生晶体管导致的电流流动。 对于所公开的实施例，通过添加P +环形成的反向偏压二极管和N +阱来防止在电压源极性反转的情况下的反向电流。

公开(公告)号：US5347169A

公开(公告)日：1994-09-13

申请号：US941736

申请日：1992-09-08

申请人： Donald R. Preslar ,  Raymond L. Giordano

发明人： Donald R. Preslar ,  Raymond L. Giordano

IPC分类号： G05F1/56 ,  H03K17/08 ,  H03K17/16 ,  H03K17/695 ,  H01H47/00

CPC分类号： H03K17/165

摘要： A circuit in which the source-to-drain conduction path of a power switching transistor is connected in series with an inductive load between first and second power terminals includes a voltage transient clamping transistor having its source-to-drain conduction path connected between the drain and gate of the switching transistor. In response to a turn-off signal applied to the gate of the switching transistor, a transient voltage is generated at the drain of the switching transistor. When the transient voltage at the drain of the power switching transistor exceeds a predetermined value, the clamping transistor is turned-on. The conduction of the clamping transistor limits the voltage rise at the drain of the switching transistor and tends to maintain the switching transistor conducting temporarily to aid in the discharge of the energy stored in the inductive load. A unidirectional conducting element connected in series with the clamping transistor ensures that only current of a polarity to discharge the inductive load flows through the clamping transistor.

摘要翻译： 其中电源开关晶体管的源极 - 漏极导通路径与第一和第二电源端子之间的感性负载串联连接的电路包括电压瞬态钳位晶体管，其源极 - 漏极导电路径连接在漏极 和开关晶体管的栅极。 响应于施加到开关晶体管的栅极的截止信号，在开关晶体管的漏极处产生瞬态电压。 当功率开关晶体管的漏极处的瞬态电压超过预定值时，钳位晶体管导通。 钳位晶体管的导通限制了开关晶体管的漏极处的电压上升，并且倾向于保持开关晶体管暂时导通以帮助放电存储在感性负载中的能量。 与钳位晶体管串联连接的单向导电元件确保仅电流负载的电流流过钳位晶体管。

公开(公告)号：US07518430B2

公开(公告)日：2009-04-14

申请号：US11091843

申请日：2005-03-28

申请人： Noel B. Dequina ,  Donald R. Preslar ,  Paul K. Sferrazza

发明人： Noel B. Dequina ,  Donald R. Preslar ,  Paul K. Sferrazza

IPC分类号： H03K17/16

CPC分类号： H02M1/36 ,  H02M1/32 ,  H02M3/156 ,  H02M3/1588 ,  Y02B70/1466

摘要： An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

摘要翻译： 过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。 包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况 初始启动系统。 响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。