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公开(公告)号：US09300202B2
公开(公告)日：2016-03-29
申请号：US13536862
申请日：2012-06-28
CPC分类号： H02M3/156 , H02M3/1588 , H02M2001/0025 , H02M2001/0032 , H02M2003/1566 , Y02B70/1466 , Y02B70/16
摘要： A regulator system with dynamic droop including a regulator control network which is adapted to control regulation of an output voltage to a reference level, a DC droop network which provides a droop signal to modify the reference level based on output load according to a predetermined DC load line, and a dynamic droop network which adjusts the droop signal to delay recovery to the predetermined DC load line within an AC load line tolerance in response to a load transient. A transient reduction network may be included to reduce transient overshoot for load insertion or release depending upon duty cycle type. The dynamic droop network adjusts the droop signal to optimize utilization of an AC delay parameter while transitioning between an AC offset voltage allowance and the predetermined DC load line.
摘要翻译： 具有动态下降的调节器系统，其包括调节器控制网络，其适于将输出电压调节到参考电平; DC下降网络，其根据预定的DC负载输出负载来提供下垂信号以修改参考电平 线路和动态下降网络，其调节下降信号以响应于负载瞬变在AC负载线路公差内延迟恢复到预定DC负载线路。 可以包括瞬态还原网络以减少负载插入或释放的瞬态过冲，这取决于占空比类型。 动态下垂网络调整下垂信号以优化AC延迟参数的利用率，同时在AC偏移电压容限和预定DC负载线之间转换。
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公开(公告)号：US20130300392A1
公开(公告)日：2013-11-14
申请号：US13536862
申请日：2012-06-28
IPC分类号： G05F1/10
CPC分类号： H02M3/156 , H02M3/1588 , H02M2001/0025 , H02M2001/0032 , H02M2003/1566 , Y02B70/1466 , Y02B70/16
摘要： A regulator system with dynamic droop including a regulator control network which is adapted to control regulation of an output voltage to a reference level, a DC droop network which provides a droop signal to modify the reference level based on output load according to a predetermined DC load line, and a dynamic droop network which adjusts the droop signal to delay recovery to the predetermined DC load line within an AC load line tolerance in response to a load transient. A transient reduction network may be included to reduce transient overshoot for load insertion or release depending upon duty cycle type. The dynamic droop network adjusts the droop signal to optimize utilization of an AC delay parameter while transitioning between an AC offset voltage allowance and the predetermined DC load line.
摘要翻译： 具有动态下降的调节器系统，其包括调节器控制网络，其适于将输出电压调节到参考电平; DC下降网络，其根据预定的DC负载输出负载来提供下垂信号以修改参考电平 线路和动态下降网络，其调节下降信号以响应于负载瞬变在AC负载线路公差内延迟恢复到预定DC负载线路。 可以包括瞬态还原网络以减少负载插入或释放的瞬态过冲，这取决于占空比类型。 动态下垂网络调整下垂信号以优化AC延迟参数的利用率，同时在AC偏移电压容限和预定DC负载线之间转换。
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公开(公告)号：US20100090668A1
公开(公告)日：2010-04-15
申请号：US12424686
申请日：2009-04-16
CPC分类号： H01L27/0688 , H01L21/823487 , H01L23/645 , H01L25/074 , H01L2224/371 , H01L2224/37147 , H01L2224/37599 , H01L2224/40245 , H01L2224/48227 , H01L2224/49171 , H01L2924/13091 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.
摘要翻译： MOSFET对的改进组合以第一和第二FET模块的叠加或堆叠关系安装，以减少MOSFET对的表面积“占地面积”。 高侧FET高和低侧FETlow的源极和漏极或相应的高侧FET高低侧FETlow的漏极直接或通过中间导电带或夹子接合在一起，以建立共同的源极/漏极或 漏极/漏极节点，用作器件的开关或相位节点。 堆叠的组织允许较低成本的封装，这导致器件的表面积占地面积的显着降低，并且相对于先前的并排组织降低寄生阻抗并且允许改进的散热。
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4.发明授权Transconductance amplifier with multi-emitter structure for current balance in a multi-phase regulator 失效具有多发射极结构的跨导放大器，用于多相调节器中的电流平衡公开(公告)号：US07015757B2
公开(公告)日：2006-03-21
申请号：US10803006
申请日：2004-03-17
申请人： Xuening Li , Thomas A. Jochum
发明人： Xuening Li , Thomas A. Jochum
CPC分类号： H03F3/45085 , H03F1/56 , H03F3/04 , H03F3/347 , H03F2200/363
摘要： A transconductance amplifier with multi-emitter structure for balancing current of a multi-phase regulator including multiple transistors, a bias current device, multiple current mirrors, and multiple current sources. Each transistor has first and second current terminals and a current control terminal receiving a corresponding one of multiple sense voltages. Each sense voltage is indicative of output inductor current of a corresponding phase of the multi-phase regulator. The bias current device is coupled to the first current terminal of each transistor. Each current mirror has an input coupled to a second current terminal of a corresponding transistor and an output coupled to a corresponding one of multiple correction nodes. Each current source is coupled to a corresponding one of multiple correction nodes. In this manner, each correction node provides a correction current for a corresponding phase of the regulator.
摘要翻译： 具有多发射极结构的跨导放大器，用于平衡多个晶体管的多相调节器的电流，偏置电流器件，多个电流镜和多个电流源。 每个晶体管具有第一和第二电流端子和电流控制端子，其接收多个感测电压中相应的一个。 每个感测电压表示多相调节器的相应相位的输出电感器电流。 偏置电流装置耦合到每个晶体管的第一电流端子。 每个电流镜具有耦合到相应晶体管的第二电流端子的输入端和耦合到多个校正节点中对应的一个的输出端。 每个电流源耦合到多个校正节点中的对应的一个。 以这种方式，每个校正节点为调节器的相应相位提供校正电流。
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5.发明授权Sample-and-hold circuit having reduced parasitic diode effects and related methods 失效采样保持电路具有减小的寄生二极管效应和相关方法
公开(公告)号：US6002277A
公开(公告)日：1999-12-14
申请号：US55561
申请日：1998-04-06
CPC分类号： G11C27/026
摘要： An integrated S/H circuit includes a first field-effect transistor (FET) formed on a substrate with a sampling capacitor, and a buffer amplifier having an input connected to the sampling capacitor and an output connectable to the body of the first FET. The buffer amplifier thereby reduces undesired effects from a parasitic diode formed by the body and sampling capacitor. More particularly, the first FET preferably has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time, and for disconnecting the input signal from the sampling capacitor during a holding time. The circuit may include one or more switches for connecting the body of the first FET to the output of the buffer amplifier during the holding time to thereby apply a holding voltage from the sampling capacitor to the body of the first FET. The holding voltage overcomes the voltage droop as would otherwise be caused by the parasitic diode. The switches may also connect the body of the first FET to a supply voltage during the sampling time. In addition, the buffer amplifier may have a substantially unity gain.
摘要翻译： 集成S / H电路包括形成在具有采样电容器的衬底上的第一场效应晶体管（FET）和具有连接到采样电容器的输入端的缓冲放大器和可连接到第一FET的本体的输出。 因此，缓冲放大器减少了由主体和采样电容器形成的寄生二极管的不期望的影响。 更具体地，第一FET优选地具有用于接收输入信号的第一导通端子，连接到采样电容器的第二导通端子和响应于在采样时间期间将输入信号连接到采样电容器的控制信号的控制端子， 并且用于在保持时间期间从采样电容器断开输入信号。 电路可以包括用于在保持时间期间将第一FET的主体连接到缓冲放大器的输出的一个或多个开关，从而将采样电容器的保持电压施加到第一FET的主体。 保持电压克服了否则将由寄生二极管引起的电压下降。 开关还可以在采样时间期间将第一FET的主体连接到电源电压。 此外，缓冲放大器可以具有基本上单位增益。
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公开(公告)号：US4761605A
公开(公告)日：1988-08-02
申请号：US944313
申请日：1986-12-22
申请人： Thomas A. Jochum
发明人： Thomas A. Jochum
CPC分类号： G01R19/18 , G01R15/185
摘要： An electronic metering circuit includes a current transformer having active feedback for maintaining core flux near zero. In one embodiment of the invention, DC offset-voltage compensation in an operational amplifier providing the active-feedback signal is accomplished using an integrator having a long time constant compared to the time constant of periodic signals. A further embodiment of the invention integrates the functions of current sensing, DC offset-voltage compensation, and part of the switching function required in the electronic metering circuit.
摘要翻译： 电子计量电路包括具有主动反馈的电流互感器，用于将磁芯磁通维持在零附近。 在本发明的一个实施例中，提供有源反馈信号的运算放大器中的直流偏移电压补偿使用与周期信号的时间常数相比具有长时间常数的积分器来实现。 本发明的另一实施例集成了电流检测，DC偏移电压补偿和电子计量电路中所需的部分开关功能的功能。
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7.发明授权System and method of predictive current feedback for switched mode regulators 有权开关模式调节器的预测电流反馈的系统和方法公开(公告)号：US08901910B2
公开(公告)日：2014-12-02
申请号：US13531751
申请日：2012-06-25
IPC分类号： G05F1/00
CPC分类号： H02M3/156 , H02M2001/0009 , H02M2001/0019
摘要： A predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.
摘要翻译： 一种用于开关模式调节器的预测电流反馈系统，包括用于对调节器的下开关进行采样电压并用于提供指示其的保持信号的采样和保持网络，以及预测电流反馈网络，其将偏移调整添加到保持信号 基于由调节器开发的脉冲控制信号的脉冲宽度的持续时间。 当下部开关打开时，可以进行采样，以提供指示电感器电流的保持值，同时脉冲控制信号为低电平。 当脉冲信号为高时，偏移调整可以响应于瞬态事件而被添加到保持信号。 偏移量可以是在标称时间段之后的每个增量时间段之后的增量值，或者可以是时变值。 脉冲信号也可以进行调整。
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公开(公告)号：US06922044B2
公开(公告)日：2005-07-26
申请号：US10673684
申请日：2003-09-29
申请人： Michael M. Walters , Xuening Li , Thomas A. Jochum
发明人： Michael M. Walters , Xuening Li , Thomas A. Jochum
CPC分类号： H02J1/102 , H02M3/156 , H02M3/1584
摘要： A multiphase ripple voltage regulator generator employs a hysteretic comparator referenced to upper and lower voltage thresholds. The hysteretic comparator monitors a master ripple voltage waveform developed across a capacitor supplied with a current proportional to the difference between the output voltage and either the input voltage or ground. The output of the hysteretic comparator generates a master clock signal that is sequentially coupled to PWM latches, the states of which define the durations of respective components of the synthesized ripple voltage. A respective PWM latch has a first state initiated by a selected master clock signal and terminated by an associated phase voltage comparator that monitors a respective phase node voltage.
摘要翻译： 多相纹波电压调节器采用基于上限和下限电压阈值的滞后比较器。 迟滞比较器监视在电容器上产生的主纹波电压波形，其电流与输出电压和输入电压或地之间的差成比例。 迟滞比较器的输出产生顺序耦合到PWM锁存器的主时钟信号，其状态限定合成纹波电压的各个分量的持续时间。 相应的PWM锁存器具有由所选择的主时钟信号启动的第一状态，并且由相关联的相位电压比较器终止，监视相应的相位节点电压。
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公开(公告)号：US06621256B2
公开(公告)日：2003-09-16
申请号：US10093197
申请日：2002-03-07
IPC分类号： G05F140
CPC分类号： H02M3/1563 , H02M3/158 , H02M2001/0032 , Y02B70/16
摘要： A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.
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公开(公告)号：US06433525B1
公开(公告)日：2002-08-13
申请号：US09846721
申请日：2001-05-01
IPC分类号： G05F140
摘要： A DC-to-DC converter has a pulse width modulator PWM) and a hysteretic (ripple) modulator. For low current loads, the hysteretic modulator is selected; for high current loads, the PWM is selected. A mode selection switch senses the polarity of the switched output voltage at the end of each switching cycle. If the polarity changes from one cycle to the next, the mode may be instantly changed to the other mode. Counters are used to record the polarity at the end of each cycle and switching from one mode to another can be delayed by the counters to prevent changing modes based on spurious output voltage fluctuations.
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