Neuromorphic arithmetic device and operating method thereof

    公开(公告)号:US11494630B2

    公开(公告)日:2022-11-08

    申请号:US16742808

    申请日:2020-01-14

    Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

    Neuromorphic arithmetic device and operating method thereof

    公开(公告)号:US11204740B2

    公开(公告)日:2021-12-21

    申请号:US16695509

    申请日:2019-11-26

    Abstract: The neuromorphic arithmetic device performs a multiply-accumulate (MAC) calculation using a multiplier and an accumulator. The neuromorphic arithmetic device includes an offset accumulator configured to receive a plurality of offset data measured a plurality of times and accumulate the plurality of offset data, a bit extractor configured to obtain average offset data by extracting at least one first bit from the plurality of accumulated offset data, and a cumulative synapse array configured to accumulate a plurality of multiplication values generated by the multiplier and output a cumulative result of the plurality of multiplication values corrected according to the average offset data.

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