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公开(公告)号：US11217299B2
公开(公告)日：2022-01-04
申请号：US16997445
申请日：2020-08-19
Inventor： Young-deuk Jeon , Seong Min Kim , Jin Kyu Kim , Joo Hyun Lee , Min-Hyung Cho , Jin Ho Han
IPC: G11C11/40 , G11C11/4076 , G11C11/4096 , G11C11/4099
Abstract: Disclosed are a device and a method for calibrating a reference voltage. The reference voltage calibrating device includes a data signal communication unit that transmits/receives a data signal, a data strobe signal receiving unit that receives a first data strobe signal and a second data strobe signal, a voltage level of the second data strobe signal being opposite to a voltage level of the first data strobe signal, and a reference voltage generating unit that sets a reference voltage for determining a data value of the data signal, based on the first data strobe signal and the second data strobe signal, and the reference voltage generating unit adjusts the reference voltage based on the first data strobe signal and the second data strobe signal.
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2.发明授权公开(公告)号：US11507799B2
公开(公告)日：2022-11-22
申请号：US16808124
申请日：2020-03-03
Inventor： Mi Young Lee , Joo Hyun Lee
Abstract: Provided is a method of operating a neural network computing device that is configured to communicate with an external memory device and execute a plurality of layers. The method includes computing a first input address, based on first layer information of a first layer among the plurality of layers and a first memory management table, and updating the first memory management table to generate a second memory management table, reading first input data to be input to the first layer from the external memory device, based on the computed first input address, computing a first output address, based on the first layer information and the second memory management table, and updating the second memory management table to generate a third memory management table, and storing first output data output from the first layer, based on the first output address, in the external memory device.
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公开(公告)号：US11494630B2
公开(公告)日：2022-11-08
申请号：US16742808
申请日：2020-01-14
Inventor： Young-deuk Jeon , Byung Jo Kim , Ju-Yeob Kim , Jin Kyu Kim , Ki Hyuk Park , Mi Young Lee , Joo Hyun Lee , Min-Hyung Cho
Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.
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公开(公告)号：US11204876B2
公开(公告)日：2021-12-21
申请号：US16953242
申请日：2020-11-19
Inventor： Byung Jo Kim , Joo Hyun Lee , Seong Min Kim , Ju-Yeob Kim , Jin Kyu Kim , Mi Young Lee
IPC: G06F12/08 , G06F12/0862 , G06N3/063 , G06F13/16 , G06F12/02
Abstract: A method for controlling a memory from which data is transferred to a neural network processor and an apparatus thereof are provided, the method including: generating prefetch information of data by using a blob descriptor and a reference prediction table after history information is input; reading the data in the memory based on the pre-fetch information and temporarily archiving read data in a prefetch buffer; and accessing next data in the memory based on the prefetch information and temporarily archiving the next data in the prefetch buffer after the data is transferred to the neural network from the prefetch buffer.
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公开(公告)号：US10438116B2
公开(公告)日：2019-10-08
申请号：US15804912
申请日：2017-11-06
Inventor： Kwang IL Oh , Sung Eun Kim , Seong Mo Park , Hyung-IL Park , Jae-Jin Lee , Joo Hyun Lee
Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.
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Patent Agency Ranking
公开(公告)号：US11455539B2
公开(公告)日：2022-09-27
申请号：US16541275
申请日：2019-08-15
Inventor： Mi Young Lee , Byung Jo Kim , Seong Min Kim , Ju-Yeob Kim , Jin Kyu Kim , Joo Hyun Lee
Abstract: An embodiment of the present invention provides a quantization method for weights of a plurality of batch normalization layers, including: receiving a plurality of previously learned first weights of the plurality of batch normalization layers; obtaining first distribution information of the plurality of first weights; performing a first quantization on the plurality of first weights using the first distribution information to obtain a plurality of second weights; obtaining second distribution information of the plurality of second weights; and performing a second quantization on the plurality of second weights using the second distribution information to obtain a plurality of final weights, and thereby reducing an error that may occur when quantizing the weight of the batch normalization layer.
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公开(公告)号：US11204740B2
公开(公告)日：2021-12-21
申请号：US16695509
申请日：2019-11-26
Inventor： Min-Hyung Cho , Young-deuk Jeon , Ki Hyuk Park , Joo Hyun Lee
Abstract: The neuromorphic arithmetic device performs a multiply-accumulate (MAC) calculation using a multiplier and an accumulator. The neuromorphic arithmetic device includes an offset accumulator configured to receive a plurality of offset data measured a plurality of times and accumulate the plurality of offset data, a bit extractor configured to obtain average offset data by extracting at least one first bit from the plurality of accumulated offset data, and a cumulative synapse array configured to accumulate a plurality of multiplication values generated by the multiplier and output a cumulative result of the plurality of multiplication values corrected according to the average offset data.
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公开(公告)号：US11025840B2
公开(公告)日：2021-06-01
申请号：US16356788
申请日：2019-03-18
Inventor： Hyun Kyu Yu , Sung Weon Kang , Young-Su Kwon , Joo Hyun Lee
Abstract: Provided is an image sensor. The image sensor includes a pixel array including pixels arranged along a first direction and a second direction, and partitioned into blocks, a converter configured to convert image signals outputted from the pixels into digital signals based on an image, and an image signal processor configured to add amplitudes of the digital signals belonging to each of the blocks to determine edge blocks among the blocks, compare the amplitudes of the digital signals to determine directions in which direction lines of the edge blocks are directed, and connect the direction lines to extract an edge of the image.
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公开(公告)号：US11003985B2
公开(公告)日：2021-05-11
申请号：US15806111
申请日：2017-11-07
Inventor： Jin Kyu Kim , Byung Jo Kim , Seong Min Kim , Ju-Yeob Kim , Mi Young Lee , Joo Hyun Lee
Abstract: Provided is a convolutional neural network system including a data selector configured to output an input value corresponding to a position of a sparse weight from among input values of input data on a basis of a sparse index indicating the position of a nonzero value in a sparse weight kernel, and a multiply-accumulate (MAC) computator configured to perform a convolution computation on the input value output from the data selector by using the sparse weight kernel.
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公开(公告)号：US11488003B2
公开(公告)日：2022-11-01
申请号：US16409437
申请日：2019-05-10
Inventor： Ju-Yeob Kim , Byung Jo Kim , Seong Min Kim , Jin Kyu Kim , Mi Young Lee , Joo Hyun Lee
Abstract: An artificial neural network apparatus and an operating method including a plurality of layer processors for performing operations on input data are disclosed. The artificial neural network apparatus may include: a flag layer processor for outputting a flag according to a comparison result between a pooling output value of a current frame and a pooling output value of a previous frame; and a controller for stopping operation of a layer processor which performs operations after the flag layer processor among the plurality of layer processors when the flag is outputted from the flag layer processor, wherein the flag layer processor is a layer processor that performs a pooling operation first among the plurality of layer processors.
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