公开(公告)号：US3860465A

公开(公告)日：1975-01-14

申请号：US32851573

申请日：1973-02-01

Applicant: ERICSSON TELEFON AB L M

Inventor： MATZNER EVA ,  STERNBECK OLAF

IPC: H01L21/00 ,  H01L29/8605 ,  H01L7/50

CPC classification number: H01L29/8605 ,  H01L21/00 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/136

Abstract: The invention refers to a method for obtaining an accurately determined high resistance in a resistor produced in a single crystalline substrate in the form of a diffused region limited in length, width and depth direction, which region is covered with an oxide layer and is provided with a first and a second window in the oxide layer for connection of two terminal contacts. According to the invention, a third window is made in the oxide layer on the top of the diffused region by means of a conventional photo-resist and etching technique whereupon the diffused region is etched in the depth direction through the third window for a predetermined time period during which such a quantity of material is removed that the resistance of the quantity of material remaining in the diffused region, measured between the first and second window, will be equal to a predetermined resistance value.

Abstract translation: 本发明涉及一种在长度，宽​​度和深度方向上限制的扩散区形式的单晶衬底中制造的电阻器中精确确定的高电阻的方法，该区域被氧化物层覆盖，并且具有 用于连接两个端子触点的氧化物层中的第一和第二窗口。 根据本发明，通过常规的光刻胶和蚀刻技术在扩散区域顶部的氧化物层中形成第三窗口，于是扩散区域沿深度方向通过第三窗口蚀刻预定时间 消除这样的材料量的时间段，即在第一和第二窗口之间测量的在扩散区域中剩余的材料的数量的电阻将等于预定的电阻值。

公开(公告)号：US3892596A

公开(公告)日：1975-07-01

申请号：US40976173

申请日：1973-10-25

Applicant: ERICSSON TELEFON AB L M

Inventor： BJORKLUND FRITZ LARS GUNNAR ,  MATZNER EVA

IPC: H01L21/24 ,  H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/06 ,  H01L7/54 ,  H01L27/02

CPC classification number: H01L27/0658 ,  H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/122

Abstract: The invention relates to a method for producing integrated circuits of high packing density in a single crystalline substrate. The method contemplates that initially the transistors of the circuits are produced with a separate subcollector in respective mutually spaced regions of the substrate in such a manner that impurity ions are introduced through a number of consecutive diffusion process steps. The regions are provided with separate isolation barriers approaching the outer edges of the respective subcollectors. Thereafter, the resistors in the circuits are produced in respective regions located adjacent the isolation barriers for the transistors in such manner that impurity ions are introduced by at least one injection process step.

Abstract translation: 本发明涉及一种在单晶衬底中制造高填充密度的集成电路的方法。 该方法考虑到最初，电路的晶体管以分离的子集电极在衬底的相互相互间隔的区域中以这样的方式产生，即杂质离子通过多个连续扩散工艺步骤被引入。 这些区域设置有接近相应子集电极的外边缘的单独的隔离屏障。 此后，电路中的电阻器以与晶体管的隔离栅极相邻的相应区域产生，使得通过至少一个注入工艺步骤引入杂质离子。