公开(公告)号：US20010038090A1

公开(公告)日：2001-11-08

申请号：US09149474

申请日：1998-09-08

Inventor： ROBERT T. RASMUSSEN ,  SURJIT S. CHADHA ,  DAVID A. CATHEY

IPC: C09K013/08

CPC classification number: H01L21/31111 ,  H01L21/02071 ,  Y10S148/051 ,  Y10T428/24802

Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.

Abstract translation: 本发明涉及一种用于半导体材料的新型蚀刻工艺，其抑制金属腐蚀，包括预处理材料，优选用表面活性剂，然后将材料暴露于包含盐，缓冲氧化物蚀刻和任选的表面活性剂 。

公开(公告)号：US5981326A

公开(公告)日：1999-11-09

申请号：US46243

申请日：1998-03-23

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/765 ,  H01L21/8238

CPC classification number: H01L21/765 ,  H01L21/761 ,  H01L21/762 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117

Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

Abstract translation: 本发明是用于电绝缘CMOS晶体管的处理方法。 该方法包括将沟道阻挡掺杂剂注入到晶体管有源区域之间的场区域中，在这些场区域上自对准相对较厚的二氧化硅，并在与场区域自对准的有源区域中提供薄氧化物。 该方法不需要任何浅沟槽隔离（STI），并且不需要局部氧化硅（LOCOS），从而导致对硅的损害很小。

公开(公告)号：US5698063A

公开(公告)日：1997-12-16

申请号：US575971

申请日：1995-12-21

Applicant: John Carlson Ames

Inventor： John Carlson Ames

IPC: H01L21/306 ,  H01L21/308 ,  C23F1/02

CPC classification number: H01L21/3083 ,  H01L21/30617 ,  Y10S148/051 ,  Y10S438/943

Abstract: A method for differentially etching an N-sided polygon aperture through a first major surface of a silicon wafer along the planes begins with depositing a mask and defining therein a first intermediate polygon aperture having at least 4N+2 sides, where N is a positive integer. At least one side is generally parallel to the plane, and the intersection of a second side and a third side of the first intermediate polygon is located generally along a major crystal axis perpendicular to the plane. The included angle between the second and third sides expands during anisotropic etching to form one of the N sides of the polygon located along the major axis perpendicular to the plane.

Abstract translation: 沿着<111>平面通过<100>硅晶片的第一主表面差异蚀刻N侧多边形孔的方法开始于沉积掩模并且在其中限定具有至少4N + 2边的第一中间多边形孔， 其中N是正整数。 至少一侧通常平行于<110>平面，并且第一中间多边形的第二侧和第三侧的交叉点大致沿垂直于<110>平面的主晶轴定位。 第二和第三面之间的夹角在各向异性蚀刻期间膨胀以形成沿着垂直于<110>平面的长轴的多边形中的一个。

公开(公告)号：US5484507A

公开(公告)日：1996-01-16

申请号：US160531

申请日：1993-12-01

Applicant: John C. Ames

Inventor： John C. Ames

IPC: H01L21/306 ,  H01L21/308 ,  B23P15/00

CPC classification number: H01L21/3083 ,  H01L21/30617 ,  Y10S148/051 ,  Y10S438/943

Abstract: A method for differentially etching an N-sided polygon aperture through a first major surface of a silicon wafer along the planes begins with depositing a mask and defining therein a first intermediate polygon aperture having at least 4N+2 sides, where N is a positive integer. At least one side is generally parallel to the plane, and the intersection of a second side and a third side of the first intermediate polygon is located generally along a major crystal axis perpendicular to the plane. The included angle between the second and third sides expands during anisotropic etching to form one of the N sides of the polygon located along the major axis perpendicular to the plane.

Abstract translation: 沿着<111>平面通过<100>硅晶片的第一主表面差异蚀刻N侧多边形孔的方法开始于沉积掩模并且在其中限定具有至少4N + 2边的第一中间多边形孔， 其中N是正整数。 至少一侧通常平行于<110>平面，并且第一中间多边形的第二侧和第三侧的交叉点大致沿垂直于<110>平面的主晶轴定位。 第二和第三面之间的夹角在各向异性蚀刻期间膨胀以形成沿着垂直于<110>平面的长轴的多边形中的一个。

公开(公告)号：US5476813A

公开(公告)日：1995-12-19

申请号：US340361

申请日：1994-11-14

Applicant: Hiroshi Naruse

Inventor： Hiroshi Naruse

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/18 ,  H01L21/331 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/20

CPC classification number: H01L21/76243 ,  H01L21/76256 ,  Y10S148/012 ,  Y10S148/051 ,  Y10S148/058 ,  Y10S148/15 ,  Y10S438/97 ,  Y10S438/977

Abstract: In a method of manufacturing a bonded semiconductor substrate, a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities of high concentration, and a silicon layer containing N-type impurities of high concentration are formed in this order on a top surface of a silicon substrate by an epitaxial growth process to form a first semiconductor substrate. A silicon oxide film is formed on a surface of a silicon substrate to form a second semiconductor substrate. The first and second semiconductor substrates are bonded to each other by heat treatment, with their top surfaces contacting each other. The first semiconductor substrate is etched from the back surface thereof until the SiGe mixed crystal layer is exposed, and the SiGe mixed crystal layer is etched until the silicon layer containing N-type impurities is exposed. This method prevents the thickness of the element forming layer from varying.

Abstract translation: 在制造接合半导体衬底的方法中，SiGe混晶层，含有N型杂质的硅层，含有高浓度N型杂质的SiGe混合层和含有高浓度N型杂质的硅层 通过外延生长工艺在硅衬底的顶表面上依次形成浓度以形成第一半导体衬底。 在硅衬底的表面上形成氧化硅膜以形成第二半导体衬底。 第一和第二半导体衬底通过热处理彼此接合，并且它们的顶表面彼此接触。 从其背面蚀刻第一半导体衬底，直到暴露SiGe混晶层，并且蚀刻SiGe混晶层，直到暴露含有N型杂质的硅层。 该方法防止元件形成层的厚度变化。

公开(公告)号：US5346851A

公开(公告)日：1994-09-13

申请号：US979117

申请日：1992-11-20

Applicant: John N. Randall ,  Gary A. Frazier ,  Rajni J. Aggarwal

Inventor： John N. Randall ,  Gary A. Frazier ,  Rajni J. Aggarwal

IPC: H01L21/66 ,  H01L21/76 ,  H01L27/06 ,  H01L29/06 ,  H01L29/68 ,  H01L21/20

CPC classification number: B82Y10/00 ,  H01L21/7605 ,  H01L27/0605 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/169 ,  Y10S438/962 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/94

Abstract: A quantum effect device implementation of the Shannon Decomposition Function in the form of a Shannon Cell is provided in which a first quantum dot logic unit (50) is coupled between the X input and the output of the Shannon Cell. A second quantum dot logic unit (52) is coupled between the Y input and the output of the Shannon Cell. The control input to the Shannon Cell is coupled to both the first and second quantum dot logic units (50 and 52) such that current flows through the appropriate quantum dot logic unit (50 or 52) depending upon the logic state of the control input.

Abstract translation: 提供了香农单元形式的香农分解函数的量子效应器件实现，其中第一量子点逻辑单元（50）耦合在香烟单元的X输入和输出之间。 第二量子点逻辑单元（52）耦合在Y输入和香农单元的输出之间。 香农盒的控制输入耦合到第一和第二量子点逻辑单元（50和52），使得电流根据控制输入的逻辑状态流过适当的量子点逻辑单元（50或52）。

公开(公告)号：US5182234A

公开(公告)日：1993-01-26

申请号：US737560

申请日：1991-07-26

Applicant: Theodore O. Meyer

Inventor： Theodore O. Meyer

IPC: H01L21/033 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/033 ,  H01L21/266 ,  H01L21/3065 ,  H01L29/41741 ,  H01L29/7396 ,  H01L29/41766 ,  H01L29/66545 ,  Y10S148/051 ,  Y10S438/942

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Abstract translation: 多晶硅的掺杂剂不透明层沉积在上基板表面上的栅极氧化物上，以在器件的制造期间用作图案定义。 它提供对连续的P和N掺杂步骤的控制，其用于在硅衬底内形成必要的操作结，并且在衬底上形成导电结构。 在上硅表面中形成沟槽，并且在栅极氧化物层的顶部淀积栅极导电层时，淀积源极导电层以与源区电接触。 使用新颖的O2-SF6等离子体蚀刻技术来调整沟槽侧壁的轮廓。 在沉积导电材料之前，在图案定义器和栅极氧化物结构的侧面上形成氧化物侧壁间隔物。 施加平面化层并用作掩模，用于选择性地去除沉积在氧化物间隔物上方的任何导电材料。 在开沟期间氧化物上的多晶硅层厚度减小，使得沉积在间隔物上方的任何导电材料向上突出以便于去除过量的导电材料。 侧壁间隔物可以单独地或与沟槽的轮廓定制组合来定尺寸，以控制源极区宽度（即寄生夹紧基底宽度）和源极导体与FET沟道的接近。 通过在它们之间形成低电阻率层来增强源极导电层与源极区之间的电接触。

公开(公告)号：US5093278A

公开(公告)日：1992-03-03

申请号：US586226

申请日：1990-09-21

Applicant: Hidenori Kamei

Inventor： Hidenori Kamei

IPC: H01S5/00 ,  H01S5/20 ,  H01S5/22 ,  H01S5/227

CPC classification number: H01S5/227 ,  H01L33/0062 ,  H01S5/2081 ,  H01S5/2201 ,  H01S5/2275 ,  Y10S148/026 ,  Y10S148/051 ,  Y10S148/095 ,  Y10S148/119 ,  Y10S148/169 ,  Y10S438/978

Abstract: According to this invention, a first cladding layer of a first conductivity type, an active layer, a second cladding layer of a second conductivity type, and a cap layer much more susceptible to side etching than the second cladding layer susceptible to side etching than the second cladding layer are sequentially grown on a (100) crystal plane of a semiconductor substrate of the first conductivity type, and a stripe-like mask extending in a direction is formed on the grown substrate with respect to each layer of the stacked substrate. This etching is performed in a crystal orientation for forming a reverse triangular mesa. However, since the cap layer is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer is formed on the etched portion by a vapor phase epitaxy method, the burying layer can be made to have a flat surface depending on crystal orientations.

公开(公告)号：US5030590A

公开(公告)日：1991-07-09

申请号：US364331

申请日：1989-06-09

Applicant: Zahra H. Amini ,  Ian S. Latchford

Inventor： Zahra H. Amini ,  Ian S. Latchford

IPC: H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/02071 ,  H01L21/32137 ,  Y10S148/051

Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving residues of polysilicon adjacent to the step and residues of a polymerized silicon/oxide-containing material adjacent the sidewalls of the masked portions of the polysilicon layer. The improvement comprises treating the integrated circuit substrate with a dilute hydroxide solution to remove both the polysilicon residues and the residues of polymerized silicon/oxide-containing material.

Abstract translation: 本发明包括改进的方法，其中在集成电路结构上的步骤上形成并用光刻胶掩模的多晶硅层被各向异性蚀刻以去除多晶硅层的暴露部分，留下与步骤 以及与多晶硅层的掩模部分的侧壁相邻的聚合的含硅/氧化物的材料的残留物。 该改进包括用稀氢氧化物溶液处理集成电路衬底以除去多晶硅残余物和聚合的含硅/氧化物材料的残余物。

公开(公告)号：US5023203A

公开(公告)日：1991-06-11

申请号：US370872

申请日：1989-06-23

Applicant: Sangsoo Choi

Inventor： Sangsoo Choi

IPC: G03F7/26 ,  G03F7/09 ,  G03F7/40 ,  H01L21/027 ,  H01L21/205 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/0274 ,  G03F7/094 ,  G03F7/40 ,  H01L21/3105 ,  H01L21/31116 ,  Y10S148/051 ,  Y10S438/947

Abstract: A method for reducing the line widths produced by patterning a semiconduc substrate with a multilayer resist mask employs a `spacer`-forming oxide layer which is non-selectively formed over the mask structure after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a `spacer` or `stringer` portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.

Abstract translation: 通过使用多层抗蚀剂掩模对半导体衬底进行图案化而产生的线宽减小的方法采用在用于暴露下部抗蚀剂层的孔已形成之后，在掩模结构之上非选择性地形成“间隔物”的氧化物层 多层掩模的上部，但在蚀刻下抗蚀剂层之前。 对氧化物层进行干式系统蚀刻，以垂直去除氧化物层的材料直到下抗蚀剂层的表面。 由于氧化层的实质阶梯覆盖，沿着掩模上部的原始孔径的侧壁保持“间隔”或“纵梁”部分，从而降低了曝光窗口的尺寸。 将该侧壁间隔物保持为掩模结构的组成部分允许较窄的线宽度复制在下面的基底中。