公开(公告)号：US5162256A

公开(公告)日：1992-11-10

申请号：US646794

申请日：1991-01-31

申请人： Holger Jurgensen

发明人： Holger Jurgensen

IPC分类号： H01L21/205 ,  H01L21/20 ,  H01L21/203 ,  H01L21/22 ,  H01L21/225

CPC分类号： H01L21/2258 ,  H01L21/22 ,  Y10S148/037 ,  Y10S438/933

摘要： A multiplicity of thin layers are applied on top of each other having alternately comparatively high concentrations of charge carriers and no doping. The thickness and the concentration of charge carriers of the individual layers being are proportioned in such a manner that the desired low concentration of charge carriers is yielded by averaging the multiplicity of layers.

摘要翻译： PCT No.PCT / DE90 / 00425 Sec。 371日期1991年1月31日 102（e）日期1991年1月31日PCT Filed 1990年6月2日PCT公布。 出版物WO90 / 15435 日期为1990年12月13日。多个薄层施加在具有交替相对较高浓度的电荷载流子并且不掺杂的彼此之上。 各层的电荷载流子的厚度和浓度按照这样的方式成比例，即通过对多个层进行平均而产生期望的低浓度电荷载流子。

公开(公告)号：US4902633A

公开(公告)日：1990-02-20

申请号：US191461

申请日：1988-05-09

申请人： Bertrand F. Cambou

发明人： Bertrand F. Cambou

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732

CPC分类号： H01L29/0821 ,  H01L21/74 ,  H01L21/761 ,  H01L29/10 ,  H01L29/36 ,  Y10S148/011 ,  Y10S148/037

摘要： A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surrounding the buried layer. The buried layer serves as a collector and it is surrounded by an isolation area. The top two epitaxial layers are of a conductivity type opposite to that of the substrate with the upper most epitaxial layer having a higher dopant density than does the middle epitaxial layer. A master mask is used to provide self-alignment between the isolation area, a collector plug which makes contact to the buried layer, and a base region.

公开(公告)号：US4888782A

公开(公告)日：1989-12-19

申请号：US216832

申请日：1988-07-08

申请人： Syoichi Kakimoto

发明人： Syoichi Kakimoto

IPC分类号： H01S5/00 ,  H01S5/16 ,  H01S5/20

CPC分类号： H01L33/0062 ,  H01S5/162 ,  H01S5/20 ,  H01S5/2059 ,  Y10S148/037 ,  Y10S148/095

摘要： A buried stripe semiconductor light emitting device and a method for producing the device in which the buried stripe functions as an internal resonator, and the device has window regions interposed between the resonator and facets on the external surface of the device. A first phase crystal growth is conducted in which a first cladding layer is grown on a doped substrate. Thereafter, a doped stripe of impurities is introduced into the first cladding layer in electrical contact with the doped substrate. The doped stripe extends longitudinally but terminates short of the facets so that later out-diffusion from the doped stripe will form the window regions. A second phase crystal growth is then conducted which buries the doped stripe internal to the semiconductor, i.e., not projecting through any external surface. The second phase crystal growth comprises an active layer, a second cladding layer and a contact layer successively grown on the first cladding layer. Impurities from the buried doped stripe are out-diffused into the active layer to the boundary between the active layer and the seocnd cladding layer to form the resonator, leaving windows interposed between the resonator ends and the facets.

摘要翻译： 掩埋条纹半导体发光器件及其制造方法，其中掩埋条用作内部谐振器，并且该器件具有介于谐振器和器件外表面上的刻面之间的窗口区域。 进行第一相晶体生长，其中在掺杂衬底上生长第一覆层。 此后，掺杂的杂质杂质被引入到与掺杂衬底电接触的第一覆层中。 掺杂的条带纵向延伸但是终止于小面，使得稍后从掺杂条纹的扩散将形成窗口区域。 然后进行第二相晶体生长，将掺杂的条纹埋入半导体内部，即不通过任何外部表面突出。 第二相晶体生长包括在第一覆层上连续生长的有源层，第二覆层和接触层。 来自埋入掺杂条纹的杂质从有源层扩散到有源层和包层之间的边界以形成谐振器，从而将窗口插入到谐振器端部和小平面之间。

公开(公告)号：US4853339A

公开(公告)日：1989-08-01

申请号：US224962

申请日：1988-07-27

申请人： Tak-Kin Chu ,  Francisco Santiago

发明人： Tak-Kin Chu ,  Francisco Santiago

IPC分类号： H01L21/363 ,  H01L31/032 ,  H01L31/108 ,  H01L31/18

CPC分类号： H01L31/108 ,  H01L21/0242 ,  H01L21/02551 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02568 ,  H01L21/02631 ,  H01L31/0324 ,  H01L31/18 ,  Y10S148/037 ,  Y10S148/063 ,  Y10S148/072 ,  Y10S148/14 ,  Y10S438/93

摘要： In a process of preparing an infrared sensitive photodiode comprising the eps of(1) forming by vacuum deposition an epitaxial layer of a semiconductor alloy material selected from the group consisting of PbS, PbSe, PbTe, PbS.sub.x Se.sub.1-x, PbS.sub.x Te.sub.1-x, PbSe.sub.x Te.sub.1-x, Pb.sub.y Sn.sub.1-y S, Pb.sub.y Sn.sub.1-y Se, Pb.sub.y Sn.sub.1-y Te, Pb.sub.y Sn.sub.1-y S.sub.x, Pb.sub.y Sn.sub.1-y S.sub.x Te.sub.1-x, Pb.sub.y Sn.sub.1-y Se.sub.x Te.sub.1-x, Pb.sub.z Cd.sub.1-z S, Pb.sub.z Cd.sub.1-z Se, Pb.sub.z Cd.sub.1-z Te, Pb.sub.z Cd.sub.1-z S.sub.x Se.sub.1-x, Pb.sub.z Cd.sub.1-z S.sub.x Te.sub.1-x, and Pb.sub.z Cd.sub.1-z Se.sub.x Te.sub.1-x, wherein 0

公开(公告)号：US4824798A

公开(公告)日：1989-04-25

申请号：US117593

申请日：1987-11-05

申请人： Robert D. Burnham ,  Robert L. Thornton

发明人： Robert D. Burnham ,  Robert L. Thornton

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/203

CPC分类号： H01L21/2258 ,  H01L21/182 ,  Y10S148/015 ,  Y10S148/034 ,  Y10S148/037 ,  Y10S148/059 ,  Y10S148/097 ,  Y10S148/11

摘要： A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e., at temperatures that are into the range of annealing temperature, e.g. about 500.degree.-900.degree. C., preferably 700.degree.-850.degree. C., so that cracking due to thermal strain or compressive stress will not occur on subsequent high temperature annealing thereby providing reproducible, uniform impurity diffusion into III-V structures. A particular application of bilayer composite source is in impurity induced disordering (IID).

摘要翻译： 薄膜双层复合源包括沉积的杂质源层，例如， Si或Sb，重掺杂有扩散使能剂，例如。 并且用钝化层盖住，例如。 Si 3 N 4，SiO 2，AlN或SiO x N y。 在优选实施例中，薄膜双层复合源包括在As源的存在下在超过500℃的温度下沉积的所述结构的表面上的Si层，以使层的厚度范围 5％-20％的原子量和薄层的Si 3 N 4在超过500℃的温度沉积在Si层上，其厚度仅足以防止Ga和As的扩散，该厚度可以是约400 -700 ANGSTROM。 使用该双层复合材料源作为III-V结构的扩散源的一个重要方面是复合源最初在高于500℃的高温下沉积，即在退火范围内的温度 温度，例如 约500-900℃，优选700-850℃，从而在随后的高温退火中不会发生由于热应变或压应力引起的裂纹，从而提供可再现的，均匀的杂质扩散到III-V结构中。 双层复合材料的特殊应用是杂质诱导无序（IID）。

公开(公告)号：US4717588A

公开(公告)日：1988-01-05

申请号：US812557

申请日：1985-12-23

申请人： Syd R. Wilson ,  Wayne M. Paulson ,  Charles J. Varker

发明人： Syd R. Wilson ,  Wayne M. Paulson ,  Charles J. Varker

IPC分类号： H01L21/22 ,  H01L21/265 ,  B05D3/14

CPC分类号： H01L21/26506 ,  H01L21/221 ,  Y10S148/037 ,  Y10S148/062 ,  Y10S438/917

摘要： A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively placing of a metal dopant in a region of the device or circuit. This aids in increasing the manufacturing yields of the switching device, and increases the number of active traps for minority carriers.

摘要翻译： 通过使用快速热加热装置提供了将金属掺杂剂扩散到半导体开关器件中的方法。 该方法提供了用于在器件或电路的区域中选择性地放置金属掺杂剂的过程。 这有助于提高开关器件的制造成本，并且增加少数载流子的主动阱的数量。

公开(公告)号：US4003036A

公开(公告)日：1977-01-11

申请号：US624868

申请日：1975-10-23

申请人： Fredrick Benjamin Jenne

发明人： Fredrick Benjamin Jenne

IPC分类号： G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/07 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L27/10876 ,  G11C11/404 ,  H01L23/522 ,  H01L27/0733 ,  H01L27/10823 ,  H01L29/7827 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/168

摘要： A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively thin diffusion of N material spaced directly above the buried layer, forming a recess that passes through the thin N layer and the epitaxial layer into the thicker buried N layer, and thereafter forming a gate within the recess.

摘要翻译： 一种由单元阵列组成的半导体读/写存储器，每个单元具有单个有源元件，该有源元件是形成在凹槽中的IGFET器件，其中一个源极或漏极区域位于位于掩埋存储电容器的正上方以及其另一个源极或漏极区域 。 每个器件的栅极连接到阵列中的地址线，并且横向扩散位线将器件的漏极互连在对准和间隔开的单元中。 通过地址线施加的电压在其连接的位线也被激活时激活门以对其埋入的电容器进行充电并存储信号。 存储电荷的读出由常规方式通过连接的位线由地址线控制。 具有这种单个元件单元的阵列的存储器件可以通过在P衬底中形成N型掩埋层扩散阵列来制造，沉积在掩埋层扩散之上的轻掺杂P材料的外延层，形成相对 在掩埋层的正上方间隔N个材料的薄扩散，形成通过薄N层和外延层进入较厚的N层的凹槽，之后在凹槽内形成栅极。

公开(公告)号：US3992232A

公开(公告)日：1976-11-16

申请号：US596724

申请日：1975-07-17

申请人： Tadao Kaji ,  Osamu Yumoto ,  Michio Suzuki

发明人： Tadao Kaji ,  Osamu Yumoto ,  Michio Suzuki

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/76 ,  H01L21/22 ,  H01L27/04

CPC分类号： H01L29/0649 ,  H01L21/762 ,  H01L29/0638 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

摘要： In a method of manufacturing a semiconductor device, wherein an element forming a region of one conductivity type isolated by an oxide layer is disposed on a semiconductor substrate of the opposite conductivity type, a ring-shaped high impurity concentration region of the opposite conductivity type is formed on a portion of the semiconductor substrate so as to surround the isolated region to thereby prevent the formation of a parasitic channel and to stabilize the surface potential of the substrate.

摘要翻译： 在制造半导体器件的方法中，其中形成由氧化物层隔离的一种导电类型的区域的元件设置在相反导电类型的半导体衬底上，相反导电类型的环状高杂质浓度区域是 形成在半导体衬底的一部分上以围绕隔离区域，从而防止形成寄生沟道并稳定衬底的表面电位。

公开(公告)号：US3972754A

公开(公告)日：1976-08-03

申请号：US582336

申请日：1975-05-30

申请人： Jacob Riseman

发明人： Jacob Riseman

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/22 ,  H01L27/04

CPC分类号： H01L21/76237 ,  H01L21/76 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/122

摘要： In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in the silicon substrate comprising selectively etching recesses in a silicon substrate and thermally oxidizing the recessed portions of the silicon substrate to form regions of recessed silicon dioxide extending into the substrate. Then, a blanket introduction of impurities of opposite-type conductivity is made into the portions of the substrate remaining unoxidized, after which a layer of silicon of said opposite-type conductivity is epitaxially deposited on the substrate surface. Next, utilizing appropriate silicon nitride masking, recesses are etched into the silicon epitaxial layer in registration with the now buried regions of recessed silicon dioxide in the substrate. Then, the recessed portions of the silicon epitaxial layer are thermally oxidized to the extent sufficient to form regions of recessed silicon dioxide extending through said epitaxial layer into registered contact respectively with the regions of recessed silicon dioxide formed in the substrate.

摘要翻译： 在集成电路的制造中，提供了一种用于在硅衬底中形成介电隔离区域的方法，包括选择性地蚀刻硅衬底中的凹槽并热氧化硅衬底的凹陷部分以形成延伸到衬底中的凹陷二氧化硅的区域。 然后，对保持未氧化的基板的部分进行相对导电性的杂质的全面引入，之后在基板表面外延地沉积有相反导电性的硅层。 接下来，利用适当的氮化硅掩蔽，将凹槽蚀刻到硅衬底中的凹陷二氧化硅的现在埋入区域的对准中。 然后，硅外延层的凹陷部分被热氧化到足以形成分别延伸穿过所述外延层的凹陷二氧化硅的区域到分别与衬底中形成的凹陷二氧化硅的区域的注入接触的程度。

公开(公告)号：US3956035A

公开(公告)日：1976-05-11

申请号：US510929

申请日：1974-10-01

申请人： Hans Herrmann

发明人： Hans Herrmann

IPC分类号： H01L21/22 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L21/76 ,  H01L21/20

CPC分类号： H01L27/0826 ,  H01L21/8222 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

摘要： This relates to a process for manufacturing monolithic integrated circuits comprising at least one pair of complementary bipolar planar transistors. The pair of transistors, having two buried layers and two superimposed epitaxially deposited layers upon a semiconductor substrate body, are manufactured by deposition of an epitaxial layer having a thickness wherein the base zone of the pnp-transistor remains and is surrounded by a p-conducting zone which is diffused during the diffusion of the base zone of the npn-transistor and a portion of an insulating zone.

摘要翻译： 这涉及制造包括至少一对互补双极平面晶体管的单片集成电路的方法。 在半导体衬底主体上具有两个掩埋层和两个叠加的外延沉积层的一对晶体管通过沉积具有厚度的外延层来制造，其中pnp晶体管的基极区保留并被p导电 在npn晶体管的基极区域和绝缘区域的一部分的扩散期间扩散的区域。