公开(公告)号：US20160027914A1

公开(公告)日：2016-01-28

申请号：US14338217

申请日：2014-07-22

Applicant: Empire Technology Development LLC

Inventor： Bishnu Prasanna Gogoi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/1095 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

Abstract: Technologies are generally described for reduction of the characteristic on resistance for a transistor device. In some examples, a transistor device may include a source region, a drain region, an n-type epitaxial region between the source and drain regions, a p-type body region, and a deep p-type trench region formed below the body region. The trench region may be configured to charge compensate the n-type epitaxial region. In other examples, the characteristic on resistance may be reduced by replacing the silicon below the body region with lower resistance conductive material. A backside of a wafer that includes the transistor device may be thinned by using a support or carrier on the front side of the wafer to provide mechanical support, and etching trenches in both the substrate silicon and the epitaxial silicon located below the body region of the transistor device. The trenches may be subsequently filled with conductive material.

Abstract translation: 通常描述技术来降低晶体管器件的电阻特性。 在一些示例中，晶体管器件可以包括源极区域，漏极区域，源极和漏极区域之间的n型外延区域，p型体区域和形成在体区域下方的深p型沟槽区域 。 沟槽区域可以被配置为对n型外延区域进行电荷补偿。 在其他示例中，可以通过用较低电阻的导电材料代替体区的下面的硅来降低电阻的特性。 包括晶体管器件的晶片的背面可以通过使用晶片正面上的支撑体或载体来减薄以提供机械支撑，并且蚀刻位于所述晶体管的身体区域下方的衬底硅和外延硅中的沟槽 晶体管器件。 沟槽可随后用导电材料填充。

公开(公告)号：US20160276439A1

公开(公告)日：2016-09-22

申请号：US15169777

申请日：2016-06-01

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Bishnu Prasanna Gogoi

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7827

Abstract: Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor. In other examples, a planar area component of a body-drain junction may be reduced by forming a spherical cavity at a bottom portion of the body-drain junction and sealing the cavity with a low dielectric constant material. In further examples, a sealed cavity may be formed in an epitaxial region below the body region through formation and removal of selective buried oxide islands. In yet other examples, the output capacitance may be reduced through removal of areas in the drain region of the transistor that do not contribute to the current flow.

Abstract translation: 描述了用于降低晶体管的输出电容的技术。 在一些示例中，可以增加源极到漏极金属化的间隔，并且可以在漏极区域中的细长沟槽中采用密封气隙，以减小体区的一部分的介电常数，从而降低体区的输出电容 晶体管。 在其它实例中，通过在体 - 排出结的底部形成球形空腔并用低介电常数材料密封空腔，可以减小体 - 排出结的平面区域分量。 在另外的例子中，通过形成和去除选择性掩埋氧化物岛，可以在体区域下方的外延区域中形成密封空腔。 在其他示例中，可以通过去除晶体管的漏极区域中不对电流流动有贡献的区域来减小输出电容。

公开(公告)号：US09406750B2

公开(公告)日：2016-08-02

申请号：US14548264

申请日：2014-11-19

Applicant: Empire Technology Development LLC

Inventor： Bishnu Prasanna Gogoi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/1083 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/66681 ,  H01L29/7802 ,  H01L29/7816

Abstract: Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor. In other examples, a planar area component of a body-drain junction may be reduced by forming a spherical cavity at a bottom portion of the body-drain junction and sealing the cavity with a low dielectric constant material. In further examples, a sealed cavity may be formed in an epitaxial region below the body region through formation and removal of selective buried oxide islands. In yet other examples, the output capacitance may be reduced through removal of areas in the drain region of the transistor that do not contribute to the current flow.

Abstract translation: 描述了降低晶体管的输出电容的技术。 在一些示例中，可以增加源极到漏极金属化的间隔，并且可以在漏极区域中的细长沟槽中采用密封气隙，以减小体区的一部分的介电常数，从而降低体区的输出电容 晶体管。 在其它实例中，通过在体 - 排出结的底部形成球形空腔并用低介电常数材料密封空腔，可以减小体 - 排出结的平面区域分量。 在另外的例子中，通过形成和去除选择性掩埋氧化物岛，可以在体区域下方的外延区域中形成密封空腔。 在其他示例中，可以通过去除晶体管的漏极区域中不对电流流动有贡献的区域来减小输出电容。

公开(公告)号：US20160141362A1

公开(公告)日：2016-05-19

申请号：US14548264

申请日：2014-11-19

Applicant: Empire Technology Development LLC

Inventor： Bishnu Prasanna Gogoi

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/1083 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/66681 ,  H01L29/7802 ,  H01L29/7816

Abstract: Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor. In other examples, a planar area component of a body-drain junction may be reduced by forming a spherical cavity at a bottom portion of the body-drain junction and sealing the cavity with a low dielectric constant material. In further examples, a sealed cavity may be formed in an epitaxial region below the body region through formation and removal of selective buried oxide islands. In yet other examples, the output capacitance may be reduced through removal of areas in the drain region of the transistor that do not contribute to the current flow.

公开(公告)号：US09312382B2

公开(公告)日：2016-04-12

申请号：US14338217

申请日：2014-07-22

Applicant: Empire Technology Development LLC

Inventor： Bishnu Prasanna Gogoi

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L29/0649 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

Abstract: Technologies are generally described for reduction of the characteristic on resistance for a transistor device. In some examples, a transistor device may include a source region, a drain region, an n-type epitaxial region between the source and drain regions, a p-type body region, and a deep p-type trench region formed below the body region. The trench region may be configured to charge compensate the n-type epitaxial region. In other examples, the characteristic on resistance may be reduced by replacing the silicon below the body region with lower resistance conductive material. A backside of a wafer that includes the transistor device may be thinned by using a support or carrier on the front side of the wafer to provide mechanical support, and etching trenches in both the substrate silicon and the epitaxial silicon located below the body region of the transistor device. The trenches may be subsequently filled with conductive material.

Abstract translation: 通常描述技术来降低晶体管器件的电阻特性。 在一些示例中，晶体管器件可以包括源极区域，漏极区域，源极和漏极区域之间的n型外延区域，p型体区域和形成在体区域下方的深p型沟槽区域 。 沟槽区域可以被配置为对n型外延区域进行电荷补偿。 在其他示例中，可以通过用较低电阻的导电材料代替体区的下面的硅来降低电阻的特性。 包括晶体管器件的晶片的背面可以通过使用晶片正面上的支撑体或载体来减薄以提供机械支撑，并且蚀刻位于所述晶体管的身体区域下方的衬底硅和外延硅中的沟槽 晶体管器件。 沟槽可随后用导电材料填充。