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    Structure and method for improving storage latch susceptibility to single event upsets
    1.
    发明授权
    Structure and method for improving storage latch susceptibility to single event upsets 有权
    用于改善单个事件扰乱的存储锁存敏感性的结构和方法

    公开(公告)号：US08300452B2

    公开(公告)日：2012-10-30

    申请号：US13050052

    申请日：2011-03-17

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    IPC分类号： G11C11/00

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

    摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

    摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

    STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS
    2.
    发明申请
    STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS 有权
    改善存储容量对单一事件的可靠性的结构和方法

    公开(公告)号：US20110163365A1

    公开(公告)日：2011-07-07

    申请号：US13050052

    申请日：2011-03-17

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    IPC分类号： H01L27/092 ,  H01L21/02

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

    摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

    摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

    Structure and method for improving storage latch susceptibility to single event upsets
    3.
    发明授权
    Structure and method for improving storage latch susceptibility to single event upsets 有权
    用于改善单个事件扰乱的存储锁存敏感性的结构和方法

    公开(公告)号：US07965540B2

    公开(公告)日：2011-06-21

    申请号：US12055509

    申请日：2008-03-26

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    IPC分类号： G11C11/412

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

    摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

    摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

    STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS
    4.
    发明申请
    STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS 有权
    改善存储容量对单一事件的可靠性的结构和方法

    公开(公告)号：US20090244954A1

    公开(公告)日：2009-10-01

    申请号：US12055509

    申请日：2008-03-26

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

    IPC分类号： G11C11/40 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

    摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

    摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

    SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS
    7.
    发明申请
    SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS 有权
    使用BURIED重组中心使用混合晶体方位的基板上CMOS电路的软错误减少

    公开(公告)号：US20080157202A1

    公开(公告)日：2008-07-03

    申请号：US11618346

    申请日：2006-12-29

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

    摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

    摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

    Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers
    8.
    发明授权
    Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers 有权
    使用掩埋复合中心的具有混合晶体取向的衬底上的CMOS电路的软误差降低

    公开(公告)号：US07521776B2

    公开(公告)日：2009-04-21

    申请号：US11618346

    申请日：2006-12-29

    申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

    发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L29/04

    CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

    摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

    摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。