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公开(公告)号：US09467153B2
公开(公告)日：2016-10-11
申请号：US14691558
申请日：2015-04-20
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Steven Gregory Troyer , Daniel K. Case
CPC classification number: H03L7/091 , H03L7/0805 , H03L7/0807 , H03L7/093 , H04L7/0016 , H04L7/033
Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
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2.发明授权Low power and compact area digital integrator for a digital phase detector 有权低功耗和紧凑型数字积分器，用于数字相位检测器公开(公告)号：US09014322B2
公开(公告)日：2015-04-21
申请号：US13757665
申请日：2013-02-01
Applicant: Finisar Corporation
Inventor： The'Linh Nguyen , Steven Gregory Troyer , Daniel K. Case
CPC classification number: H03L7/091 , H03L7/0805 , H03L7/0807 , H03L7/093 , H04L7/0016 , H04L7/033
Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
Abstract translation: 在示例性实施例中，锁相环电路可以包括用于接收参考信号和源信号的第一电路。 第一电路可以产生用于示出参考信号和源信号之间的相位差的校正信号。 锁相环可以包括用于接收校正信号的第二电路。 第二电路可以产生用于演示校正信号的相位到数字转换的数字信号。 锁相环可以包括用于接收数字信号的第三电路。 第三电路可以产生用于演示数字信号的转换电压的控制信号。 锁相环可以包括用于接收控制信号的第四电路。 第四电路可以响应于控制信号产生源信号。
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公开(公告)号：US20160013800A1
公开(公告)日：2016-01-14
申请号：US14691558
申请日：2015-04-20
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Steven Gregory Troyer , Daniel K. Case
CPC classification number: H03L7/091 , H03L7/0805 , H03L7/0807 , H03L7/093 , H04L7/0016 , H04L7/033
Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
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4.发明申请LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR 有权用于数字相位检测器的低功率和紧凑型数字集成器公开(公告)号：US20130315349A1
公开(公告)日：2013-11-28
申请号：US13757665
申请日：2013-02-01
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Steven Gregory Troyer , Daniel K. Case
IPC: H04L7/00
CPC classification number: H03L7/091 , H03L7/0805 , H03L7/0807 , H03L7/093 , H04L7/0016 , H04L7/033
Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
Abstract translation: 在示例性实施例中，锁相环电路可以包括用于接收参考信号和源信号的第一电路。 第一电路可以产生用于示出参考信号和源信号之间的相位差的校正信号。 锁相环可以包括用于接收校正信号的第二电路。 第二电路可以产生用于演示校正信号的相位到数字转换的数字信号。 锁相环可以包括用于接收数字信号的第三电路。 第三电路可以产生用于演示数字信号的转换电压的控制信号。 锁相环可以包括用于接收控制信号的第四电路。 第四电路可以响应于控制信号产生源信号。
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