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公开(公告)号：US09160327B2
公开(公告)日：2015-10-13
申请号：US13901140
申请日：2013-05-23
申请人： FUJITSU LIMITED
IPC分类号： G06F13/28 , H03K17/16 , H03K5/1252 , H03K19/003
CPC分类号： H03K17/16 , H03K5/1252 , H03K19/00361
摘要： A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.
摘要翻译： 包括用于接收输入信号的输入端子和用于输出输出信号的输出端子的半导体器件包括与输入端子串联连接的延迟元件，并且每个延迟元件将延迟分配给从输入端子输入的输入信号，连接到 延迟元件的输出侧，并且每个用于基于用于选择延迟元件的输出信号中的一个的选择信号来选择延迟元件的输出信号之一，以将输出信号中选择的一个输出信号返回到输出端子;以及 延迟电路，其对应于选择器设置，并且每个用于使输入的选择信号的切换输入到相应的一个选择器中，以在切换输入到用作信号转折点的相应选择器中的相应一个的输入信号的信号电平之后发生 。
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公开(公告)号：US08698536B2
公开(公告)日：2014-04-15
申请号：US13778229
申请日：2013-02-27
申请人： Fujitsu Limited
IPC分类号： H03H11/26
摘要： Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is “0”, and outputs a signal input to a first input terminal when the set signal is “1”, and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal.
摘要翻译： 包括串联连接的多个单元延迟电路和根据设定信号不反相输出输出信号的输出电路。 第一单位延迟电路包括：当设定信号为“0”时输出输入到第二输入端子的信号的选择器，当设定信号为“1”时，输出输入到第一输入端子的信号， 从第二输出端反相并输出选择器的输出。 第二单元延迟电路包括：反相器，其将输入到第一输入端子的信号和从第一输出端子输出的反相器和当设定信号为“0”时输出到第二输入端子的信号的选择器，并且输出 当设定信号从第二输出端子“1”时，逆变器的输出。
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公开(公告)号：US20130254434A1
公开(公告)日：2013-09-26
申请号：US13901140
申请日：2013-05-23
申请人： FUJITSU LIMITED
IPC分类号： H03K17/16
CPC分类号： H03K17/16 , H03K5/1252 , H03K19/00361
摘要： A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.
摘要翻译： 包括用于接收输入信号的输入端子和用于输出输出信号的输出端子的半导体器件包括与输入端子串联连接的延迟元件，并且每个延迟元件将延迟分配给从输入端子输入的输入信号，连接到 延迟元件的输出侧，并且每个用于基于用于选择延迟元件的输出信号中的一个的选择信号来选择延迟元件的输出信号之一，以将输出信号中选择的一个输出信号返回到输出端子;以及 延迟电路，其对应于选择器设置，并且每个用于使输入的选择信号的切换输入到相应的一个选择器中，以在切换输入到用作信号转折点的相应选择器中的相应一个的输入信号的信号电平之后发生 。
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