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公开(公告)号：US07698151B2
公开(公告)日：2010-04-13
申请号：US10335910
申请日：2003-01-03
申请人： Francesco Gozzo , Emmett M. Perry, Jr. , William W. Walker , Michael J. Maselli , James N. Sutton, Jr.
发明人： Francesco Gozzo , Emmett M. Perry, Jr. , William W. Walker , Michael J. Maselli , James N. Sutton, Jr.
IPC分类号： G06Q10/00
摘要： The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement.
摘要翻译： 为了呈现公司的账单，陈述等而提供的灾难恢复技术，在发生灾难时提供影响公司打印邮件传送操作或其他现有邮件系统的电子文档呈现。 从与打印邮件传送操作相关联的系统接收包含电子文档的文件，并将文档存储在数据库中。 系统最好使用公司现有的数据文件。 如果需要，这些文件可以被转换成与一种或多种电子传送方法兼容的格式。 灾难恢复系统以电子形式向公司的客户提供文件的通知和/或数据，例如作为电子邮件（包含部分或全部文档数据的通知或消息）作为电子邮件的文档附件，通过 一个网站，并可能通过电话语音通知。
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公开(公告)号：US20090037762A1
公开(公告)日：2009-02-05
申请号：US10335910
申请日：2003-01-03
申请人： Francesco Gozzo , Emmett M. Perry,, JR. , William W. Walker , Michael J. Maselli , James N. Sutton,, JR.
发明人： Francesco Gozzo , Emmett M. Perry,, JR. , William W. Walker , Michael J. Maselli , James N. Sutton,, JR.
摘要： The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement.
摘要翻译： 为了呈现公司的账单，陈述等而提供的灾难恢复技术，在发生灾难时提供影响公司打印邮件传送操作或其他现有邮件系统的电子文档呈现。 从与打印邮件传送操作相关联的系统接收包含电子文档的文件，并将文档存储在数据库中。 系统最好使用公司现有的数据文件。 如果需要，这些文件可以被转换成与一种或多种电子传送方法兼容的格式。 灾难恢复系统以电子形式向公司的客户提供文件的通知和/或数据，例如作为电子邮件（包含部分或全部文档数据的通知或消息）作为电子邮件的文档附件，通过 一个网站，并可能通过电话语音通知。
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公开(公告)号：US08432995B2
公开(公告)日：2013-04-30
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译： 在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位 数据位。
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公开(公告)号：US20100090733A1
公开(公告)日：2010-04-15
申请号：US12511352
申请日：2009-07-29
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译： 在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。 在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。
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公开(公告)号：US20080192873A1
公开(公告)日：2008-08-14
申请号：US12022725
申请日：2008-01-30
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
摘要翻译： 在一个实施例中，一种方法包括接收包括多个比特的数据信号。 该方法还包括产生时钟信号。 从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点 样品。 如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。 如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。
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6.发明授权公开(公告)号：US07405593B2
公开(公告)日：2008-07-29
申请号：US11265550
申请日：2005-11-01
IPC分类号： H03K19/094
CPC分类号： H04L25/0282 , H03K3/356191 , H03K3/35625 , H04L25/0272 , H04L25/0294 , Y10T83/2037 , Y10T83/204
摘要： Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.
摘要翻译： 本发明公开了采用差分电流模式感测的片上全球电信令系统和方法，与传统的逆变器中继器相比具有降低的延迟和能量消耗。 本发明可以用于点到点连接以及N到1连接。
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公开(公告)号：US07256621B2
公开(公告)日：2007-08-14
申请号：US11089956
申请日：2005-03-25
申请人： Yolin Lih , William W. Walker
发明人： Yolin Lih , William W. Walker
IPC分类号： H03K19/20
CPC分类号： H03K19/0013 , H03K19/0963
摘要： Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.
摘要翻译： 公开了用于电子电路的保持器电路，其选择性地将中间电路节点的电压电平维持在期望的水平。 在一个示例性实施例中，保持器晶体管或者从中间节点提供电流或漏极电流，以响应于这样做的信号来维持期望的电压电平。 保持器电路针对泄漏电流起作用，该泄漏电流从节点排出电流或将电流提供给节点。 电流设定晶体管与保持器晶体管串联耦合，以将通过保持器电路的最大电流设置为与该漏电流相关的值，优选地跟踪漏电流。 利用这种结构，电流设定晶体管能够跟踪由制造工艺的变化引起的漏电流的变化，从而提供动态泄漏补偿。
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公开(公告)号：US08138798B2
公开(公告)日：2012-03-20
申请号：US12511340
申请日：2009-07-29
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.
摘要翻译： 在一个实施例中，电路包括用于接收具有第一相位的第一输入信号的第一电路输入端; 用于接收具有第二相位的第二输入信号的第二电路输入; 用于输出电路输出信号的电路输出; 第一混频器单元，包括第一混频器单元输入，第二混频器单元输入和第一混频器单元输出; 以及包括第三混频器单元输入，第四混频器单元输入和第二混频器单元输出的第二混频器单元。 第一电路输入连接到第一和第二混频器单元输入，第二电路输入连接到第二和第四混频器单元输入，并且组合第一和第二混频器单元输出以提供电路输出。 电路输出信号的电流与第一和第二相之间的相位偏移成比例。
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公开(公告)号：US20110310692A1
公开(公告)日：2011-12-22
申请号：US12819082
申请日：2010-06-18
申请人： Scott McLeod , William W. Walker
发明人： Scott McLeod , William W. Walker
IPC分类号： G11C8/04
摘要： In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.
摘要翻译： 在一个实施例中，一种方法包括响应于在包括多个字的存储器阵列处的写入使能信号的断言，顺序地并且以第一时钟频率将数据从存储器阵列的开始处写入存储器阵列 直到内存数组已满。 该方法包括，与基于在存储器阵列处接收到的读取地址的数据相比，以与从存储器阵列读取数据的第一时钟频率相比慢的第二时钟频率异步地和以第二时钟频率写入数据。
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公开(公告)号：US08058914B2
公开(公告)日：2011-11-15
申请号：US12511352
申请日：2009-07-29
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译： 在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。 在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。
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