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Patent Agency Ranking
公开(公告)号：US11979041B2
公开(公告)日：2024-05-07
申请号：US17129857
申请日：2020-12-21
Inventor： Ni Sun , Stephen W Bryson
CPC classification number: H02J7/00304 , H02H7/18 , H02J7/0031
Abstract: A fully integrated circuit configuration that can be utilized to prevent abnormal discharge or overcharge in ultra-portable electronic systems is described. This battery protection integrated circuit can be enhanced by the addition of traditional battery protection schemes such as current limiting, overcurrent clamping, under voltage lock out and over voltage protection. This battery protection scheme utilizes a high side switch approach utilizing an ultra-low leakage PMOS power switch rather than the traditional low side NMOS switching.
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公开(公告)号：US20170288660A1
公开(公告)日：2017-10-05
申请号：US15632243
申请日：2017-06-23
Inventor： Stephen W. Bryson , Ni Sun
IPC: H03K17/16
CPC classification number: H03K17/161 , H03K17/0822 , H03K17/20 , H03K2217/0036 , H03K2217/0054
Abstract: Described are apparatus and methods for a load switch with reset and deep sleep capability. The slew rate control methods of the PMOS load switches contained in the load switch configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated reset and deep sleep functions allow the user to control the basic timing control of the voltages that are required by the system and to save battery power in an extended deep sleep mode such as storage and shipping.
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公开(公告)号：US20210210969A1
公开(公告)日：2021-07-08
申请号：US17129857
申请日：2020-12-21
Inventor： Ni Sun , Stephen W. Bryson
Abstract: A fully integrated circuit configuration that can be utilized to prevent abnormal discharge or overcharge in ultra-portable electronic systems is described. This battery protection integrated circuit can be enhanced by the addition of traditional battery protection schemes such as current limiting, overcurrent clamping, under voltage lock out and over voltage protection. This battery protection scheme utilizes a high side switch approach utilizing an ultra-low leakage PMOS power switch rather than the traditional low side NMOS switching.
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4.发明公开公开(公告)号：US20240291298A1
公开(公告)日：2024-08-29
申请号：US18657764
申请日：2024-05-07
Inventor： Ni Sun , Stephen W Bryson
CPC classification number: H02J7/00306 , H01M10/44 , H02J7/00302 , H02J7/00304 , H02J7/00309 , H02J7/0034 , H02J7/0063 , H02J7/0069
Abstract: A fully integrated circuit configuration that can be utilized to prevent abnormal overdischarge and overcharge in ultra-portable electronic systems is described. This battery protection integrated circuit can be enhanced by the addition of traditional battery protection schemes such as current limiting, overcurrent clamping, under voltage lock out and over voltage protection. This battery protection scheme utilizes a high side switch approach utilizing an ultra-low leakage PMOS power switch rather than the traditional low side NMOS switching.
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公开(公告)号：US20170359057A1
公开(公告)日：2017-12-14
申请号：US15669690
申请日：2017-08-04
Inventor： Stephen W. Bryson , Ni Sun
CPC classification number: H03K17/161 , H02H3/033 , H02H3/18 , H02H3/202 , H02H3/243 , H02H5/04 , H02J7/345
Abstract: Described are apparatus and methods for control of multi-channel load switches with synchronized power up/down timing sequences. The slew rate control methods of the PMOS load switches contained in the N Multi-channel configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated controller allows the user to program the power on/off sequences of each of the load switch channels by simply using a single or multiple input enable input pins.
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