公开(公告)号：US20150325467A1

公开(公告)日：2015-11-12

申请号：US14272787

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Kun Ho Ahn ,  Bernd Hintze ,  Frank Koschinsky

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用原子层沉积（ALD）工艺和物理气相沉积（PVD）工艺在半导体衬底上形成覆盖金属化层的金属线的势垒层。 将衬垫形成材料沉积在阻挡层上方以形成衬垫。 导电金属沉积在衬垫上方。

公开(公告)号：US09177858B1

公开(公告)日：2015-11-03

申请号：US14272787

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Kun Ho Ahn ,  Bernd Hintze ,  Frank Koschinsky

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用原子层沉积（ALD）工艺和物理气相沉积（PVD）工艺在半导体衬底上形成覆盖金属化层的金属线的势垒层。 将衬垫形成材料沉积在阻挡层上方以形成衬垫。 导电金属沉积在衬垫上方。