公开(公告)号：US20190326413A1

公开(公告)日：2019-10-24

申请号：US15960965

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arkadiusz Malinowski ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/08

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

公开(公告)号：US10546943B2

公开(公告)日：2020-01-28

申请号：US15960965

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arkadiusz Malinowski ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3065

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

公开(公告)号：US09812573B1

公开(公告)日：2017-11-07

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US20170330970A1

公开(公告)日：2017-11-16

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.