公开(公告)号：US12131904B2

公开(公告)日：2024-10-29

申请号：US17934220

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

CPC classification number: H01L21/02433 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US20240332366A1

公开(公告)日：2024-10-03

申请号：US18614522

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Carlo RIVA

IPC: H01L29/16 ,  C30B28/02 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L29/1608 ,  C30B28/02 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02378 ,  H01L21/02433 ,  H01L29/04

Abstract: A polycrystalline silicon carbide (SiC) substrate with a density gradient between a first side of the polycrystalline SiC substrate and a second side of the polycrystalline SiC substrate opposite to the first side. A first density at the first side of the polycrystalline SiC substrate is less than a second density at the second side of the polycrystalline SiC substrate. The polycrystalline SiC substrate with the density gradient may be formed by forming a polycrystalline SiC base substrate with a sintering process followed by a post-sintering process. For example, the post sintering process may be at least one of the following of: applying a first temperature to the first side and a second temperature to the second side of the polycrystalline SiC substrate and performing a chemical vapor deposition (CVD) process to impregnate further silicon (Si) and carbon (C) atoms into the polycrystalline SiC base substrate.

公开(公告)号：US12051585B2

公开(公告)日：2024-07-30

申请号：US17432444

申请日：2019-02-28

Applicant: TIANJIN UNIVERSITY

Inventor： Lei Ma ,  Walter Alexander De Heer ,  Peixuan Ji ,  Kaimin Zhang ,  Jian Zhao ,  Mei Zhao

IPC: C30B29/02 ,  B28D5/04 ,  C30B1/02 ,  H01L21/02

CPC classification number: H01L21/02013 ,  B28D5/045 ,  C30B1/026 ,  C30B29/02 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02527 ,  H01L21/0262

Abstract: The present invention provides a control method to epitaxial growth monolayer graphene, in which a monolayer graphene is epitaxially grown on a non-polar crystal face at arbitrary angle of a non-polar crystal face SiC substrate, thereby utilizing the non-polar crystal face to manipulate the electrical transport properties of graphene. A monolayer graphene having ballistic transport properties can be epitaxially grown at arbitrary angle of non-polar crystal face SiC substrate by the above-mentioned control method.

公开(公告)号：US12020924B2

公开(公告)日：2024-06-25

申请号：US17053655

申请日：2019-03-15

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Takaya Miyase ,  Tsutomu Hori

IPC: H01L21/02 ,  C30B29/36 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L21/02378 ,  C30B29/36 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/1608

Abstract: The composite defect includes an extended defect and a basal plane dislocation. The extended defect includes a first region extending in a direction from an origin located at a boundary between the silicon carbide substrate and the silicon carbide epitaxial film, and a second region extending along a direction. The first region has a width in the direction that increases from the origin toward the second region. The basal plane dislocation includes a third region continuous to the origin and extending along the direction, and a fourth region extending along a direction intersecting the direction. When an area of the main surface is a first area, and an area of a quadrangle circumscribed around the composite defect is a second area, a value obtained by dividing the second area by the first area is not more than 0.001.

公开(公告)号：US11990336B2

公开(公告)日：2024-05-21

申请号：US17296281

申请日：2019-08-05

Applicant: SUMCO CORPORATION

Inventor： Masayuki Ishibashi ,  Midori Yoshida ,  Daisuke Maruoka

IPC: H01L21/02 ,  C30B25/10 ,  H01L21/306

CPC classification number: H01L21/02532 ,  C30B25/10 ,  H01L21/02433 ,  H01L21/0262 ,  H01L21/30625

Abstract: To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1100° C. to 1135° C. and growing the epitaxial layer in the vapor phase at a growth rate of 2.0 μm/min to 3.0 μm/min.

公开(公告)号：US11982016B2

公开(公告)日：2024-05-14

申请号：US17471395

申请日：2021-09-10

Applicant: TAMURA CORPORATION ,  NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY

Inventor： Ken Goto ,  Kohei Sasaki ,  Akinori Koukitu ,  Yoshinao Kumagai ,  Hisashi Murakami

IPC: C30B25/16 ,  C23C16/40 ,  C23C16/448 ,  C30B25/02 ,  C30B29/16 ,  H01L21/02 ,  H01L29/04 ,  H01L29/24

CPC classification number: C30B25/165 ,  C23C16/40 ,  C23C16/4488 ,  C30B25/02 ,  C30B29/16 ,  H01L21/02414 ,  H01L21/02433 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/0259 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02634 ,  H01L29/04 ,  H01L29/24

Abstract: As one embodiment, the present invention provides a method for growing a β-Ga2O3-based single crystal film by using HYPE method. The method includes a step of exposing a Ga2O3-based substrate to a gallium chloride-based gas and an oxygen-including gas, and growing a β-Ga2O3-based single crystal film on a principal surface of the Ga2O3-based substrate at a growth temperature of not lower than 900° C.

公开(公告)号：US11948795B2

公开(公告)日：2024-04-02

申请号：US17052889

申请日：2019-12-09

Applicant: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Inventor： Myung Mo Sung ,  Lynn Lee ,  Jin Won Jung ,  Jong Chan Kim

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  C30B25/02 ,  C30B29/16 ,  H01L21/30 ,  H01L29/04 ,  H01L29/20 ,  H01L29/22 ,  H01L29/786 ,  H01L33/12 ,  H01L33/16 ,  H01L33/28 ,  H01L33/32

CPC classification number: H01L21/0262 ,  C23C16/407 ,  C23C16/45525 ,  C30B25/02 ,  C30B29/16 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/02609 ,  H01L21/30 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/78696 ,  H01L33/12 ,  H01L33/16 ,  H01L33/28 ,  H01L33/32

Abstract: Provided are a method for manufacturing a single-crystal semiconductor layer. The method of manufacturing the single crystalline semiconductor layer includes performing a unit cycle multiple times, wherein the unit cycle includes a metal precursor pressurized dosing operation in which a metal precursor is adsorbed on a surface of a single crystalline substrate by supplying the metal precursor onto the single crystalline substrate while an outlet of a chamber in which the single crystalline substrate is loaded is closed such that a reaction pressure in the chamber is increased; a metal precursor purge operation; a reactive gas supplying operation in which a reactive gas is supplied into the chamber to cause a reaction of the reactive gas with the metal precursor adsorbed on the single crystalline substrate after the metal precursor purge operation; and a reactive gas purge operation.

公开(公告)号：US20240105449A1

公开(公告)日：2024-03-28

申请号：US18374744

申请日：2023-09-29

Applicant: MITSUBISHI CHEMICAL CORPORATION

Inventor： Yutaka MIKAWA ,  Hideo FUJISAWA ,  Tae MOCHIZUKI ,  Hideo NAMITA ,  Shinichiro KAWABATA

IPC: H01L21/02 ,  C30B7/10 ,  C30B29/38 ,  C30B29/40 ,  C30B33/06 ,  H01L29/20 ,  H01L33/00

CPC classification number: H01L21/02389 ,  C30B7/10 ,  C30B29/38 ,  C30B29/406 ,  C30B33/06 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/2003 ,  H01L33/0093 ,  H01L21/02433

Abstract: A conductive C-plane GaN substrate has a resistivity of 2×10−2 Ω·cm or less or an n-type carrier concentration of 1×1018 cm−3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.

公开(公告)号：US20240087888A1

公开(公告)日：2024-03-14

申请号：US18465835

申请日：2023-09-12

Applicant: ASM IP Holding, B.V.

Inventor： Rami Khazaka

IPC: H01L21/02 ,  C30B25/10 ,  H01L21/3065

CPC classification number: H01L21/02532 ,  C30B25/10 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065

Abstract: A method for forming a Si-comprising epitaxial layer selectively on a substrate is disclosed. Embodiments of the presently described method comprise performing a cyclic deposition and etch processes, thereby forming selectively the Si-comprising epitaxial layer. The described method may help to form source/drain regions of field effect transistors in a bottom-up manner.

公开(公告)号：US20240063016A1

公开(公告)日：2024-02-22

申请号：US18281994

申请日：2022-03-31

Applicant: SINO NITRIDE SEMICONDUCTOR CO., LTD.

Inventor： Junjie REN ,  Shuai WANG

IPC: H01L21/02 ,  H01L21/683

CPC classification number: H01L21/02389 ,  H01L21/0254 ,  H01L21/02433 ,  H01L21/02609 ,  H01L21/6836 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: The present disclosure provides a method for fabricating a self-supporting gallium nitride substrate, comprising: 1) providing a composite substrate including a sapphire substrate and a gallium nitride film; 2) forming a temporary bonding layer on the gallium nitride film; 3) bonding a transfer substrate to the composite substrate by means of the temporary bonding layer; 4) stripping the sapphire substrate by means of a laser stripping process; 5) performing weak bonding on a receiving substrate and the gallium nitride film, and detaching the transfer substrate from the gallium nitride film by invalidating the temporary bonding layer, and 6) epitaxially growing a gallium nitride epitaxial layer on the gallium nitride film, and invalidating the weak bonding by means of the lattice mismatch stress and/or the thermal mismatch stress between the gallium nitride film and the gallium nitride epitaxial layer and the receiving substrate, so as to realize separation between the gallium nitride film and the receiving substrate. The present application can effectively overcome the defect that the thickness of a heterojunction gallium nitride epitaxial layer is limited due to lattice mismatch and thermal mismatch, improve the quality of the self-supporting gallium nitride substrate, and reduce the manufacturing cost of the self-supporting gallium nitride substrate.