公开(公告)号：US20170330970A1

公开(公告)日：2017-11-16

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US20140248749A1

公开(公告)日：2014-09-04

申请号：US13783685

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7847

Abstract: A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.

Abstract translation: 一种方法包括提供包括设置在半导体区域上的栅极结构的半导体结构。 进行离子注入工艺。 在离子注入工艺中，与栅极结构相邻的半导体区域的第一部分和与栅极结构相邻的半导体区域的第二部分是非晶化的，从而在栅极结构附近形成第一非晶化区域和第二非晶化区域。 进行原子层沉积工艺。 原子层沉积工艺在半导体结构上沉积具有固有应力的材料层。 进行原子层沉积工艺的至少一部分的温度，并且选择原子层沉积工艺的至少一部分的持续时间，使得第一非晶化区域和第二非晶化区域在 原子层沉积工艺。

公开(公告)号：US20170125610A1

公开(公告)日：2017-05-04

申请号：US14928595

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/49 ,  H01L27/06 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

公开(公告)号：US09136266B2

公开(公告)日：2015-09-15

申请号：US13943229

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/78

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract translation: 在各个方面，提供了形成半导体器件和半导体器件的方法。 在本文的一些说明性实施例中，硅/锗层设置在半导体衬底上。 在硅/锗层上形成至少一个绝缘材料层。 在进行热退火处理之后，在随后的处理顺序中除去至少一个绝缘材料层，使得硅/锗层至少部分暴露。 在随后施加的另外的处理顺序中，在暴露的硅/锗层上形成栅电极。

公开(公告)号：US20140264349A1

公开(公告)日：2014-09-18

申请号：US14184863

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer ,  Alban Zaka

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

Abstract translation: 在本发明的方面，公开了一种形成半导体器件的方法，其中在制造期间的早期阶段形成非晶区域，并且非晶区域在随后的处理序列期间保守，并且提供具有非晶区域的中间半导体器件结构 在制造的早期阶段。 这里，在半导体衬底上提供栅极结构，并且在栅极结构附近形成非晶区。 源极/漏极延伸区域或源极/漏极区域形成在非晶区域中。 在一些说明性实施例中，可以将氟注入到非晶区域中。 在形成源极/漏极延伸区域和/或源极/漏极区域之后，执行快速热退火工艺。

公开(公告)号：US20140264347A1

公开(公告)日：2014-09-18

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20180198000A1

公开(公告)日：2018-07-12

申请号：US15913344

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/66 ,  H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

公开(公告)号：US09960284B2

公开(公告)日：2018-05-01

申请号：US14928595

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L27/06 ,  H01L29/161

CPC classification number: H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

Abstract: A semiconductor structure includes a varactor and a field effect transistor. The varactor includes a body region that includes a semiconductor material and a first gate structure over the body region. The body region is doped to have a first conductivity type. The first gate structure includes a first gate insulation layer and a first work function adjustment metal layer. The field effect transistor includes a source region, a channel region, a drain region and a second gate structure over the channel region. The source region and the drain region are doped to have a second conductivity type that is opposite to the first conductivity type. The second gate structure includes a second gate insulation layer and a second work function adjustment metal layer. The first work function adjustment metal layer and the second work function adjustment metal layer include substantially the same metal.

公开(公告)号：US09396950B2

公开(公告)日：2016-07-19

申请号：US14184863

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer ,  Alban Zaka

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

Abstract translation: 在本发明的方面中，公开了一种形成半导体器件的方法，其中在制造期间的早期形成非晶区域，并且非晶区域在随后的处理序列期间保守，并且提供具有非晶区域的中间半导体器件结构 在制造的早期阶段。 这里，在半导体衬底上提供栅极结构，并且在栅极结构附近形成非晶区。 源极/漏极延伸区域或源极/漏极区域形成在非晶区域中。 在一些说明性实施例中，可以将氟注入到非晶区域中。 在形成源极/漏极延伸区域和/或源极/漏极区域之后，执行快速热退火工艺。

公开(公告)号：US09231045B2

公开(公告)日：2016-01-05

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。