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    Methods, apparatus, and system for reducing leakage current in semiconductor devices
    1.
    发明授权
    Methods, apparatus, and system for reducing leakage current in semiconductor devices 有权

    公开(公告)号：US10546943B2

    公开(公告)日：2020-01-28

    申请号：US15960965

    申请日：2018-04-24

    申请人： GLOBALFOUNDRIES INC.

    发明人： Arkadiusz Malinowski ,  Jagar Singh

    IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3065

    摘要： Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

    INSULATING INDUCTOR CONDUCTORS WITH AIR GAP USING ENERGY EVAPORATION MATERIAL (EEM)
    2.
    发明申请
    INSULATING INDUCTOR CONDUCTORS WITH AIR GAP USING ENERGY EVAPORATION MATERIAL (EEM) 审中-公开

    公开(公告)号：US20200013551A1

    公开(公告)日：2020-01-09

    申请号：US16550431

    申请日：2019-08-26

    申请人： GLOBALFOUNDRIES INC.

    发明人： Sunil K. Singh ,  Jagar Singh

    IPC分类号： H01F41/063 ,  H01F41/12 ,  H01F5/00 ,  H01F5/06 ,  H01F41/34 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02 ,  H01L21/00

    摘要： A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

    Laterally diffused field effect transistor and a method of manufacturing the same
    3.
    发明授权
    Laterally diffused field effect transistor and a method of manufacturing the same 有权

    公开(公告)号：US10475921B2

    公开(公告)日：2019-11-12

    申请号：US15888195

    申请日：2018-02-05

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Jagar Singh

    IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

    摘要： An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.

    Hybrid material electrically programmable fuse and methods of forming
    4.
    发明授权
    Hybrid material electrically programmable fuse and methods of forming 有权

    公开(公告)号：US10461029B2

    公开(公告)日：2019-10-29

    申请号：US15686230

    申请日：2017-08-25

    申请人： GLOBALFOUNDRIES INC.

    发明人： Chun Yu Wong ,  Jagar Singh

    IPC分类号： H01L23/525 ,  H01L23/528 ,  H01L21/762 ,  H01L29/161

    摘要： Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).

    LDMOS finFET structures with shallow trench isolation inside the fin
    6.
    发明授权
    LDMOS finFET structures with shallow trench isolation inside the fin 有权

    公开(公告)号：US10290712B1

    公开(公告)日：2019-05-14

    申请号：US15797606

    申请日：2017-10-30

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

    IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

    摘要： Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.

    LDMOS FinFET structures with trench isolation in the drain extension
    9.
    发明授权
    LDMOS FinFET structures with trench isolation in the drain extension 有权

    公开(公告)号：US10164006B1

    公开(公告)日：2018-12-25

    申请号：US15797701

    申请日：2017-10-30

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/02

    摘要： Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A first isolation region is arranged between the first fin and the second fin. A body region of a first conductivity type is arranged partially in the substrate and partially in the second fin. A drain region of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. A source region is arranged within the body region in the first fin. A gate structure is arranged to overlap with a portion of the first fin. A second isolation region is arranged within the first fin, and is spaced along the first fin from the first isolation region.

    Fin-based RF diodes
    10.
    发明授权
    Fin-based RF diodes 有权

    公开(公告)号：US09960248B2

    公开(公告)日：2018-05-01

    申请号：US15616653

    申请日：2017-06-07

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Jagar Singh

    IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L29/861 ,  H01L21/265 ,  H01L29/06 ,  H01L21/762 ,  H01L27/08

    CPC分类号： H01L21/76224 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

    摘要： Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.