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公开(公告)号:US10312154B2
公开(公告)日:2019-06-04
申请号:US15705888
申请日:2017-09-15
Applicant: GLOBALFOUNDRIES INC.
Inventor: Ruilong Xie , Steven Bentley , Puneet Harischandra Suvarna , Chanro Park , Min Gyu Sung , Lars Liebmann , Su Chen Fan , Brent Anderson
IPC: H01L21/8238 , H01L29/66 , H01L29/06 , H01L29/78 , H01L21/84 , H01L21/8234
Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
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公开(公告)号:US20190252267A1
公开(公告)日:2019-08-15
申请号:US16390232
申请日:2019-04-22
Applicant: GLOBALFOUNDRIES INC.
Inventor: Ruilong Xie , Steven Bentley , Puneet Harischandra Suvarna , Chanro Park , Min Gyu Sung , Lars Liebmann , Su Chen Fan , Brent Anderson
IPC: H01L21/8238 , H01L29/66 , H01L29/78 , H01L21/84 , H01L29/06 , H01L21/8234
CPC classification number: H01L21/823821 , H01L21/823431 , H01L21/845 , H01L29/0653 , H01L29/6656 , H01L29/66583 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/78642
Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.
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公开(公告)号:US09786788B1
公开(公告)日:2017-10-10
申请号:US15204259
申请日:2016-07-07
Applicant: GLOBALFOUNDRIES INC.
Inventor: Brent Anderson , Edward J. Nowak
IPC: H01L29/66 , H01L29/786 , H01L29/423
CPC classification number: H01L29/78642 , H01L29/42392 , H01L29/66742
Abstract: A semiconductor device includes a plurality of vertical-transport fin field effect transistors that are arranged at a locally-variable fin pitch. Within a first region of the device, a first plurality of fins are arranged at a first pitch (d1), and within a second region of the device, a second plurality of fins are arranged as a second pitch (d2) less than the first pitch. The second plurality of fins share merged source, drain and gate regions, while the source, drain and gate regions for the first plurality of fins are unmerged.
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