公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10418484B1

公开(公告)日：2019-09-17

申请号：US15920748

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8232 ,  H01L27/112 ,  H01L27/24 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/786

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

公开(公告)号：US10249535B2

公开(公告)日：2019-04-02

申请号：US15433188

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Chanemougame ,  Lars Liebmann ,  Nigel Cave

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/78

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

公开(公告)号：US20190006232A1

公开(公告)日：2019-01-03

申请号：US16103372

申请日：2018-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L21/768 ,  H01L29/40 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02

Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

公开(公告)号：US10079173B2

公开(公告)日：2018-09-18

申请号：US15285092

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L29/768 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76861 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401

Abstract: One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate and forming a metallization blocking structure in the layer of insulating material at a location that is in a path of a metallization trench to be formed in the layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material. The method also includes forming the metallization trench in the layer of insulating material on opposite sides of the metallization blocking structure and forming a conductive metallization line in the metallization trench on opposite sides of the metallization blocking structure.

公开(公告)号：US10074564B2

公开(公告)日：2018-09-11

申请号：US15878486

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L23/522 ,  H01L29/40 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US20180166335A1

公开(公告)日：2018-06-14

申请号：US15878486

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US10796056B2

公开(公告)日：2020-10-06

申请号：US16014287

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory A. Northrop ,  Lionel Riviere-Cazaux ,  Lars Liebmann ,  Kai Sun ,  Norihito Nakamoto

IPC: G06F30/00 ,  G06F30/392 ,  G03F1/36 ,  G06F30/398 ,  H01L21/78 ,  G06F111/04 ,  G06F111/20

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

公开(公告)号：US20190287863A1

公开(公告)日：2019-09-19

申请号：US15920748

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.