公开(公告)号：US10475904B2

公开(公告)日：2019-11-12

申请号：US15868004

申请日：2018-01-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Hiroaki Niimi ,  Steven Bentley ,  Romain Lallement ,  Brent A. Anderson ,  Junli Wang ,  Muthumanickam Sankarapandian

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/11 ,  H01L21/8238

摘要： A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

公开(公告)号：US10461196B2

公开(公告)日：2019-10-29

申请号：US15662526

申请日：2017-07-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC分类号： H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.

公开(公告)号：US20190279990A1

公开(公告)日：2019-09-12

申请号：US15917027

申请日：2018-03-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Bipul C. Paul ,  Joseph Versaggi ,  Steven Bentley

IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L51/05 ,  H01L29/78 ,  H01L29/06 ,  H01L27/28

摘要： Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.

公开(公告)号：US20190252267A1

公开(公告)日：2019-08-15

申请号：US16390232

申请日：2019-04-22

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8234

CPC分类号： H01L21/823821 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78642

摘要： A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190214484A1

公开(公告)日：2019-07-11

申请号：US15868004

申请日：2018-01-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Hiroaki Niimi ,  Steven Bentley ,  Romain Lallement ,  Brent A. Anderson ,  Junli Wang ,  Muthumanickam Sankarapandian

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/092

摘要： A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

公开(公告)号：US10332969B2

公开(公告)日：2019-06-25

申请号：US16167081

申请日：2018-10-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788

摘要： A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

公开(公告)号：US09991352B1

公开(公告)日：2018-06-05

申请号：US15651282

申请日：2017-07-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ali Razavieh ,  Ruilong Xie ,  Steven Bentley

IPC分类号： H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/42364 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

摘要： A method that includes forming a patterned stack of materials comprising at least one channel semiconductor material layer and first and second layers of sacrificial material positioned above and below, respectively, the at least one channel semiconductor material layer, forming a replacement gate cavity above the patterned stack of materials and performing an etching process through the gate cavity to selectively remove at least a portion of the first and second layers of sacrificial material relative to the at least one channel semiconductor material layer. The method further includes performing a second etching process to form a reduced-thickness portion of the channel semiconductor material layer that has a final thickness that is less than the initial thickness and forming a replacement gate structure around at least the reduced-thickness portion of the channel semiconductor material layer.

公开(公告)号：US09972494B1

公开(公告)日：2018-05-15

申请号：US15351747

申请日：2016-11-15

申请人： GLOBALFOUNDRIES INC.

发明人： Steven Bentley ,  Ruilong Xie

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L21/28123 ,  H01L21/26513 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

公开(公告)号：US20170317169A1

公开(公告)日：2017-11-02

申请号：US15652873

申请日：2017-07-18

申请人： GLOBALFOUNDRIES INC.

发明人： Steven Bentley ,  Deepak Nayak

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

公开(公告)号：US09805988B1

公开(公告)日：2017-10-31

申请号：US15366514

申请日：2016-12-01

申请人： GLOBALFOUNDRIES INC.

发明人： Steven Bentley ,  Guillaume Bouche

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L29/36 ,  H01L29/66 ,  H01L21/266 ,  H01L21/324 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088

CPC分类号： H01L21/845 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

摘要： One aspect of the disclosure is directed to a method of forming a semiconductor structure including: forming a fin over a substrate within a device region, the fin including alternating layers of a sacrificial material and a semiconductor material, and including a lower channel region; forming a dopant-containing layer over the fin and the substrate; exposing an upper portion of the fin by removing the dopant-containing layer from the upper portion of the fin; removing the sacrificial material from the fin thereby suspending the semiconductor material within the fin between a pair of spacers and over the lower channel region of the fin; performing an anneal to drive in dopants from the dopant-containing layer to the lower channel region of the fin; and forming an active gate over the lower channel region of the fin and substantially surrounding the suspended semiconductor material over the lower channel region of the fin.