公开(公告)号：US20160163739A1

公开(公告)日：2016-06-09

申请号：US15040307

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

Abstract translation: 本公开的方面提供了形成在包括隔离鳍片的块状衬底上的多栅极场效应晶体管（FET）及其形成方法。 在一个实施例中，多栅极FET包括：形成在本体衬底上的多个硅鳍结构，每个硅鳍结构包括体区，源区和漏区; 其中每个硅鳍结构的主体区域的底部部分包括将本体区域与本体衬底隔离的倾斜形状，并且其中所述多个硅鳍结构体经由所述源极区域的至少一部分附接到所述本体衬底， 或至少一部分漏极区域，或两者。

公开(公告)号：US09461149B2

公开(公告)日：2016-10-04

申请号：US14484916

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li ,  Xiaoping Liang ,  Kai Zhao

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.

Abstract translation: 提供了制造具有降低的栅极电阻的堆叠的纳米线场效应晶体管（FET）的方法。 可以通过首先形成交替的牺牲材料层和纳米线材料层的材料堆叠来提供堆叠的纳米线FET中的纳米线堆叠。 随后去除材料堆叠中的牺牲材料层和选定的纳米线材料层以增加两个活性纳米线材料层之间的垂直距离。

公开(公告)号：US09287178B2

公开(公告)日：2016-03-15

申请号：US13632237

申请日：2012-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li

IPC: H01L21/20 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

Abstract translation: 本公开的方面提供了形成在包括隔离鳍片的块状衬底上的多栅极场效应晶体管（FET）及其形成方法。 在一个实施例中，多栅极FET包括：形成在本体衬底上的多个硅鳍结构，每个硅鳍结构包括体区，源区和漏区; 其中每个硅鳍结构的主体区域的底部部分包括将本体区域与本体衬底隔离的倾斜形状，并且其中所述多个硅鳍结构体经由所述源极区域的至少一部分附接到所述本体衬底， 或至少一部分漏极区域，或两者。

公开(公告)号：US09954002B2

公开(公告)日：2018-04-24

申请号：US15040307

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li

IPC: H01L27/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.