公开(公告)号：US20170083661A1

公开(公告)日：2017-03-23

申请号：US14862652

申请日：2015-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

公开(公告)号：US20160378903A1

公开(公告)日：2016-12-29

申请号：US14751222

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathan Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Gregory M. Schaeffer ,  Stephen G. Shuma ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5018 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract translation: 方法和系统将集成电路设计接收到计算机化设备中，并对集成电路设计进行分析，以识别集成电路设计部分的物理特征的特征。 这样的方法和系统通过以下方式确定是否查看集成电路设计的一部分的定时值对制造过程变量，电压变量和温度变量（PVT变量）的敏感度：评估部分的物理特征的特性之间的关系 的集成电路设计生成指标值; 并且基于指标值是否在表使用过滤器值范围内，或者：计算定时值对PVT变量的灵敏度; 或从查找表中查找先前确定的定时值对PVT变量的敏感度。

公开(公告)号：US09519747B1

公开(公告)日：2016-12-13

申请号：US14751222

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathan Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Gregory M. Schaeffer ,  Stephen G. Shuma ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5018 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract translation: 方法和系统将集成电路设计接收到计算机化设备中，并对集成电路设计进行分析，以识别集成电路设计部分的物理特征的特征。 这样的方法和系统通过以下方式确定是否查看集成电路设计的一部分的定时值对制造过程变量，电压变量和温度变量（PVT变量）的敏感度：评估部分的物理特征的特性之间的关系 的集成电路设计生成指标值; 并且基于指标值是否在表使用过滤器值范围内，或者：计算定时值对PVT变量的灵敏度; 或从查找表中查找先前确定的定时值对PVT变量的敏感度。

公开(公告)号：US09619609B1

公开(公告)日：2017-04-11

申请号：US14862652

申请日：2015-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.