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    Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling
    1.
    发明授权
    Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling 有权
    使用基于时序闭合的自适应频率缩放来控制集成电路芯片温度的系统和方法

    公开(公告)号：US09552447B2

    公开(公告)日：2017-01-24

    申请号：US14695091

    申请日：2015-04-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

    IPC: G06F9/455 ,  G06F17/50 ,  G06F1/10

    CPC classification number: G06F17/5031 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

    Abstract: Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

    Abstract translation: 公开了使用基于预定温度 - 频率设置的频率缩放来控制集成电路芯片温度的系统和方法。 在集成电路芯片操作期间，控制器使可变时钟信号发生器基于集成电路芯片的温度和预定的温度 - 频率设置来调整协调集成电路芯片的操作的时钟信号的频率。 温度 - 频率设置是预先确定的，以确保调整后的时钟信号的频率保持足够高以满足芯片性能规格，但足够低以防止温度升高到高于预定最大温度以限制 能量消耗。 还公开了一种在定时分析期间产生这种温度 - 频率设置的方法。

    INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WINDOW-AWARE TIMING ANALYSIS
    3.
    发明申请
    INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WINDOW-AWARE TIMING ANALYSIS 有权

    公开(公告)号：US20170083661A1

    公开(公告)日：2017-03-23

    申请号：US14862652

    申请日：2015-09-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

    Abstract: Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

    Integrated circuit chip design methods and systems using process window-aware timing analysis
    6.
    发明授权
    Integrated circuit chip design methods and systems using process window-aware timing analysis 有权

    公开(公告)号：US09619609B1

    公开(公告)日：2017-04-11

    申请号：US14862652

    申请日：2015-09-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

    Abstract: Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

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