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11 条记录 (耗时 0.013 秒)

    Double bandwidth algorithmic memory array
    1.
    发明授权
    Double bandwidth algorithmic memory array 有权

    公开(公告)号：US09870163B2

    公开(公告)日：2018-01-16

    申请号：US15140016

    申请日：2016-04-27

    申请人： GLOBALFOUNDRIES INC.

    发明人： Igor Arsovski ,  Eric D. Hunt-Schroeder ,  Mark W. Kuemerle

    IPC分类号： G06F3/06

    CPC分类号： G06F11/108

    摘要： The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

    INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WINDOW-AWARE TIMING ANALYSIS
    2.
    发明申请
    INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WINDOW-AWARE TIMING ANALYSIS 有权

    公开(公告)号：US20170083661A1

    公开(公告)日：2017-03-23

    申请号：US14862652

    申请日：2015-09-23

    申请人： GLOBALFOUNDRIES INC.

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

    摘要： Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

    DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY
    3.
    发明申请
    DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY 有权

    公开(公告)号：US20170315738A1

    公开(公告)日：2017-11-02

    申请号：US15140016

    申请日：2016-04-27

    申请人： GLOBALFOUNDRIES INC.

    发明人： Igor Arsovski ,  Eric D. Hunt-Schroeder ,  Mark W. Kuemerle

    IPC分类号： G06F3/06

    CPC分类号： G06F11/108

    摘要： The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

    Integrated circuit chip design methods and systems using process window-aware timing analysis
    5.
    发明授权
    Integrated circuit chip design methods and systems using process window-aware timing analysis 有权

    公开(公告)号：US09619609B1

    公开(公告)日：2017-04-11

    申请号：US14862652

    申请日：2015-09-23

    申请人： GLOBALFOUNDRIES INC.

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Susan K. Lichtensteiger ,  Mark W. Kuemerle ,  Jeffrey G. Hemmett

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

    摘要： Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

    Interconnect structure
    6.
    发明授权
    Interconnect structure 有权

    公开(公告)号：US10381304B2

    公开(公告)日：2019-08-13

    申请号：US15664484

    申请日：2017-07-31

    申请人： GLOBALFOUNDRIES INC.

    发明人： Luke England ,  Mark W. Kuemerle

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L23/528

    摘要： The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.

    Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling
    8.
    发明授权
    Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling 有权
    使用基于时序闭合的自适应频率缩放来控制集成电路芯片温度的系统和方法

    公开(公告)号：US09552447B2

    公开(公告)日：2017-01-24

    申请号：US14695091

    申请日：2015-04-24

    申请人： GLOBALFOUNDRIES INC.

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

    IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F1/10

    CPC分类号： G06F17/5031 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

    摘要： Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

    摘要翻译： 公开了使用基于预定温度 - 频率设置的频率缩放来控制集成电路芯片温度的系统和方法。 在集成电路芯片操作期间，控制器使可变时钟信号发生器基于集成电路芯片的温度和预定的温度 - 频率设置来调整协调集成电路芯片的操作的时钟信号的频率。 温度 - 频率设置是预先确定的，以确保调整后的时钟信号的频率保持足够高以满足芯片性能规格，但足够低以防止温度升高到高于预定最大温度以限制 能量消耗。 还公开了一种在定时分析期间产生这种温度 - 频率设置的方法。

    INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING AND METHOD OF FORMING SAME
    9.
    发明申请
    INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING AND METHOD OF FORMING SAME 审中-公开

    公开(公告)号：US20190287879A1

    公开(公告)日：2019-09-19

    申请号：US15921852

    申请日：2018-03-15

    申请人： GLOBALFOUNDRIES INC.

    发明人： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

    IPC分类号： H01L23/488 ,  H01L25/065

    摘要： An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.