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    Electromigration-aware integrated circuit design methods and systems
    1.
    发明授权
    Electromigration-aware integrated circuit design methods and systems 有权

    公开(公告)号：US09740815B2

    公开(公告)日：2017-08-22

    申请号：US14922256

    申请日：2015-10-26

    Applicant: GlobalFoundries Inc.

    Inventor： Jeanne P. Bickford ,  Alok Chandra ,  Anand Kumaraswamy ,  Sandeep Prajapati ,  Venkatasreekanth Prudvi

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78

    Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

    Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling
    3.
    发明授权
    Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling 有权
    使用基于时序闭合的自适应频率缩放来控制集成电路芯片温度的系统和方法

    公开(公告)号：US09552447B2

    公开(公告)日：2017-01-24

    申请号：US14695091

    申请日：2015-04-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

    IPC: G06F9/455 ,  G06F17/50 ,  G06F1/10

    CPC classification number: G06F17/5031 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

    Abstract: Disclosed are a system and method that control integrated circuit chip temperature using frequency scaling based on predetermined temperature-frequency settings. During integrated circuit chip operation, a controller causes a variable clock signal generator to adjust the frequency of a clock signal that coordinates operations of an integrated circuit chip based on the temperature of the integrated circuit chip and on predetermined temperature-frequency settings. The temperature-frequency settings are predetermined in order to ensure that the frequency of the clock signal, as adjusted, remains sufficiently high to meet a chip performance specification, but sufficiently low to prevent the temperature from rising above a predetermined maximum temperature in order to limit power consumption. Also disclosed is a method of generating such temperature-frequency settings during timing analysis.

    Abstract translation: 公开了使用基于预定温度 - 频率设置的频率缩放来控制集成电路芯片温度的系统和方法。 在集成电路芯片操作期间，控制器使可变时钟信号发生器基于集成电路芯片的温度和预定的温度 - 频率设置来调整协调集成电路芯片的操作的时钟信号的频率。 温度 - 频率设置是预先确定的，以确保调整后的时钟信号的频率保持足够高以满足芯片性能规格，但足够低以防止温度升高到高于预定最大温度以限制 能量消耗。 还公开了一种在定时分析期间产生这种温度 - 频率设置的方法。

    Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation
    4.
    发明授权
    Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation 有权

    公开(公告)号：US10013519B2

    公开(公告)日：2018-07-03

    申请号：US15270598

    申请日：2016-09-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sudeep Mandal ,  Jeanne P. Bickford

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

    Integrated circuit chip reliability using reliability-optimized failure mechanism targeting
    6.
    发明授权
    Integrated circuit chip reliability using reliability-optimized failure mechanism targeting 有权

    公开(公告)号：US09639645B2

    公开(公告)日：2017-05-02

    申请号：US14742801

    申请日：2015-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5081

    Abstract: Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

    Systems and methods to prevent incorporation of a used integrated circuit chip into a product
    8.
    发明授权
    Systems and methods to prevent incorporation of a used integrated circuit chip into a product 有权

    公开(公告)号：US09618566B2

    公开(公告)日：2017-04-11

    申请号：US14620273

    申请日：2015-02-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jeanne P. Bickford ,  Nazmul Habib ,  Baozhen Li ,  Tad J. Wilder

    IPC: G01R31/28 ,  G06F21/57 ,  H05K13/08

    CPC classification number: G01R31/2851 ,  G01R31/2813 ,  G06F21/575 ,  H05K13/0486 ,  H05K13/08

    Abstract: In the systems and methods, an identifier is generated for a printed circuit board (PCB), chips are connected to the PCB, and corresponding sets of programmable bits on the chips are programmed to match specific sections of the identifier. Due to the generation of the identifier and the programming of the corresponding sets of programmable bits on the chips to match specific sections of the identifier, the validity of the chips can be verified at any time during product life. For example, for each chip, its set of programmable bits can be read and, then, a determination can be made as to whether that set of programmable bits is indeed programmed to match a specific section of the identifier. Operation of the PCB can be allowed when all the chips are determined to be valid and prohibited when any of the chips are determined to be invalid (e.g., previously used).

    PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION
    9.
    发明申请
    PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION 有权

    公开(公告)号：US20180082007A1

    公开(公告)日：2018-03-22

    申请号：US15270598

    申请日：2016-09-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sudeep Mandal ,  Jeanne P. Bickford

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

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