公开(公告)号：US09240406B2

公开(公告)日：2016-01-19

申请号：US14257143

申请日：2014-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai D. Feng ,  Dan Moy ,  Chengwen Pei ,  Robert R. Robison ,  Pinping Sun ,  Richard A. Wachnik ,  Ping-Chuan Wang

IPC: H01L27/07 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0733 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11206 ,  H01L29/66181 ,  H01L29/945

Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Abstract translation: 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。

公开(公告)号：US20170358691A1

公开(公告)日：2017-12-14

申请号：US15181834

申请日：2016-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Xiu ,  Chengwen Pei ,  Pinping Sun

IPC: H01L29/93 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H03L7/093 ,  H03L7/099

Abstract: Various particular embodiments include a semiconductor varactor structure including: a semiconductor substrate of a first conductivity type; a semiconductor area of a second conductivity type, different from the first conductivity type, within the semiconductor substrate; a field effect transistor (FET) structure within the semiconductor area; and a contact, contacting the semiconductor area, for applying a voltage bias to the semiconductor area.