公开(公告)号：US20150140756A1

公开(公告)日：2015-05-21

申请号：US14084756

申请日：2013-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Seong Yeol MUN ,  Bingwu LIU ,  Lun ZHAO ,  Richard J. CARTER ,  Manfred ELLER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract translation: 提供了电路制造方法，其包括例如：提供设置在衬底结构上方的一个或多个栅极结构，所述衬底结构包括第一区域和第二区域; 在所述第一区域和所述第二区域中形成延伸到所述衬底结构中的多个U形空腔，其中所述多个U形空腔中的至少一个第一空腔邻近所述第一区域中的一个栅极结构设置; 以及将所述至少一个第一空腔进一步扩展到所述衬底结构中以至少部分地切割所述一个栅极结构，而不扩展所述多个U形空腔中的至少一个第二空腔，其中形成所述多个U形空腔有助于制造 电路结构。 在一个实施例中，电路结构包括具有不同器件结构的第一和第二晶体管，第一晶体管具有比第二晶体管更高的迁移率特性。

公开(公告)号：US20190019880A1

公开(公告)日：2019-01-17

申请号：US15649227

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Seong Yeol MUN ,  Kwan-Yong LIM ,  Kijik LEE

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

公开(公告)号：US20150318280A1

公开(公告)日：2015-11-05

申请号：US14266278

申请日：2014-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Seong Yeol MUN ,  Bumhwan JEON ,  Kijik LEE

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795

Abstract: A wide-bottom contact to epitaxial structures in a non-planar semiconductor structure is provided. A starting structure includes a non-planar semiconductor structure, the structure including a semiconductor substrate, fins coupled to the substrate, and epitaxial structures (e.g., diamond-shaped silicon epitaxy) on the fins. Trenches to the epitaxial structures with roughly vertical sidewalls are created from a field oxide and photoresist. Silicide is formed on the epitaxial structures, and bottom contact portions (of metal, e.g., tungsten) are conformally created on the silicide. The vertical sidewalls allow for a wider bottom. Contact bodies are then formed on the bottom contact portions.

Abstract translation: 提供了一种与非平面半导体结构中的外延结构的宽底部接触。 起始结构包括非平面半导体结构，该结构包括半导体衬底，耦合到该衬底的鳍片，以及翅片上的外延结构（例如，菱形硅外延）。 对于具有大致垂直侧壁的外延结构的沟槽由场氧化物和光致抗蚀剂产生。 在外延结构上形成硅化物，并且在硅化物上共形地形成金属（例如钨）的底部接触部分。 垂直侧壁允许更宽的底部。 然后在底部接触部分上形成接触体。