公开(公告)号：US20190131452A1

公开(公告)日：2019-05-02

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Hong YU ,  Xinyuan DOU ,  Xusheng WU ,  Dongil CHOI ,  Edmund K. BANGHART ,  Md Khaled HASSAN

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US20180277440A1

公开(公告)日：2018-09-27

申请号：US15467536

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Zhenyu HU ,  Haiting WANG

IPC: H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.

公开(公告)号：US20170033224A1

公开(公告)日：2017-02-02

申请号：US14812653

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Zhenyu HU ,  Hong YU ,  Jinping LIU

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/7853 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66795

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract translation: 一种方法可以包括执行蚀刻工艺以限定具有第一深度的翅片沟槽，第一深度小于翅片的目标高度。 方法还可以包括形成层以保护限定翅片沟槽的侧壁。 方法还可以包括执行第二蚀刻工艺以增加散热片沟槽的深度。

公开(公告)号：US20160315084A1

公开(公告)日：2016-10-27

申请号：US14691960

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  HongLiang SHEN ,  Changyong XIAO ,  Jianhua YIN ,  Jie CHEN ,  Jin Ping LIU ,  Hong YU ,  Zhenyu HU ,  Lan YANG ,  Wanxun HE

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L29/1033

Abstract: There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

Abstract translation: 这里在一个实施例中阐述了具有第一区域和第二区域的半导体结构。 第一区域可以包括第一翅片高度的翅片，并且第二区域可以包括具有第二翅片高度的翅片。

公开(公告)号：US20160276345A1

公开(公告)日：2016-09-22

申请号：US15049391

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Bingwu LIU ,  Hui ZANG ,  Lun ZHAO

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/3083 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract translation: 公开了用于形成具有减小的场氧化物损耗的FinFET源极/漏极区域的方法以及所得到的器件。 实施例包括在硅衬底上形成由场氧化物分离的硅散热片; 凹陷场氧化物以露出硅散热片的上部; 在翅片的上部和场氧化物上方形成间隔层; 用具有间隔层的高选择性的材料填充翅片之间的空间; 凹陷材料; 在所述材料的上表面上方移除所述间隔层; 去除材料; 使翅片的上部凹陷; 并且在凹陷散热片上外延生长源极/漏极区域。

公开(公告)号：US20200035543A1

公开(公告)日：2020-01-30

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Haiting WANG ,  Hong YU ,  Laertis ECONOMIKOS

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

公开(公告)号：US20150017774A1

公开(公告)日：2015-01-15

申请号：US13938786

申请日：2013-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hua TONG ,  Hong YU ,  Jin Ping LIU ,  Hyucksoo YANG ,  Lun ZHAO ,  Chandra REDDY

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/823431 ,  H01L29/7854

Abstract: Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity.

Abstract translation: 提供了在制造半导体器件期间使用的热氧化处理方法和工艺。 一种方法包括例如：获得具有蚀刻到该装置中的至少一个腔的装置; 对所述至少一个腔进行热氧化处理; 以及清洁所述至少一个腔。 一个过程包括例如：提供具有衬底的半导体器件，衬底上的至少一个层和至少一个鳍; 在翅片上形成至少一个闸门; 掺杂鳍片以下的至少一个区域; 在该装置上施加间隔层; 蚀刻间隔层以露出栅极材料的至少一部分; 将空腔蚀刻到所述至少一个翅片中; 将成形的开口蚀刻到空腔中; 在所述至少一个腔体上进行热氧化处理; 以及在腔的内表面上生长至少一个外延层。

公开(公告)号：US20190228976A1

公开(公告)日：2019-07-25

申请号：US15876407

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Jinsheng GAO ,  Hong YU ,  Jinping LIU ,  Huang LIU

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

公开(公告)号：US20180330995A1

公开(公告)日：2018-11-15

申请号：US16026840

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan DOU ,  Hong YU ,  Zhenyu HU ,  Xing ZHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/42376

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US20150332934A1

公开(公告)日：2015-11-19

申请号：US14281359

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Xiang HU ,  Zhao LUN ,  Huang LIU

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L29/12 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/0684 ,  H01L29/12 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract translation: 诸如FinFET的非平面半导体结构的凸起结构（例如，翅片）上的光刻叠层包括旋涂非晶碳或旋涂有机平面化材料的底层，氮化物的硬掩模层 和/或旋涂层上的氧化物，硬掩模层上的可显影底部抗反射涂层（dBARC）的层和光致抗蚀剂的顶层。 蚀刻该叠层以露出和凹进凸起的结构，并且外延结构在凹槽上生长。