公开(公告)号：US09311442B2

公开(公告)日：2016-04-12

申请号：US14261632

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shayak Banerjee ,  James A. Culp ,  Ian P. Stobert

IPC: G06F17/50 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5068 ,  G06F2217/12

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.

Abstract translation: 各种实施例包括用于验证集成电路（IC）布局的计算机实现的方法，计算机程序产品和系统。 在某些情况下，方法包括验证IC布局的计算机实现的方法，该方法包括：获得关于IC布局中的至少一个物理特征的过程变化频带的数据; 确定所述IC布局中的所述至少一个物理特征的基于电压的过程变化带阈值; 基于IC布局中的至少一个物理特征的基于电压的过程变化带阈值来确定IC布局中的至少一个物理特征的过程变化带是否符合IC布局的设计规范; 以及响应于所述至少一个物理特征的所述过程变化带不符合所述设计规范的确定来修改所述IC布局。