公开(公告)号：US20140183720A1

公开(公告)日：2014-07-03

申请号：US13731305

申请日：2012-12-31

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott Beasor ,  Jay Strane ,  Man Fai Ng ,  Brett H. Engel ,  Chang Yong Xiao ,  Michael P. Belyansky ,  Tsung-Liang Chen ,  Kyung Bum Koo

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

Abstract translation: 公开了具有压缩氮化物层的半导体集成电路的制造方法。 在一个示例中，制造集成电路的方法包括在半导体衬底上沉积铝层，在铝层上沉积拉伸氮化硅层或中性氮化硅层，以及在抗拉氮化硅上沉积压缩氮化硅层 层或中性氮化硅层。 压缩氮化硅层以至少约为拉伸氮化硅层或中性氮化硅层厚度的约两倍的厚度沉积。 此外，在铝层和拉伸氮化硅层或中性氮化硅层之间的界面处，或者在拉伸氮化硅层或中性氮化硅层与压缩氮化物层之间的界面处没有分层存在。

公开(公告)号：US11239119B2

公开(公告)日：2022-02-01

申请号：US16585348

申请日：2019-09-27

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Heng Wu ,  Jay Strane ,  Hemanth Jagannathan ,  Lan Yu ,  Tao Li

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

Abstract: A method of forming a vertical channel semiconductor structure, comprises forming a source/drain layer in contact with at least one semiconductor fin. A first sacrificial layer is formed over the source/drain layer. A second sacrificial layer is formed over the first sacrificial layer. A trench is formed in the second sacrificial layer to expose a portion of the first sacrificial layer. After forming the second sacrificial layer, the first sacrificial layer is selectively removed to form a cavity under the second sacrificial layer. A spacer layer is then formed within the cavity.