公开(公告)号：US20180145073A1

公开(公告)日：2018-05-24

申请号：US15786164

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven BENTLEY ,  Bipul C. PAUL

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

公开(公告)号：US20150170735A1

公开(公告)日：2015-06-18

申请号：US14105939

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. PAUL ,  Randy W. MANN ,  Sangmoon J. KIM

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

Abstract translation: 提供了具有提高存取晶体管物理放置对称性的双端口静态随机存取存储器（SRAM）位单元结构。 比特单元结构可以包括例如两对并行下拉晶体管。 比特单元结构还可以包括形成第一端口的通过栅极晶体管PGLA和PGRA，以及形成第二端口的通过栅极晶体管PGLB和PGRB。 通路栅极晶体管PGLA和PGLB可以彼此相邻，并且位单元结构的第一侧，以及栅极晶体管PGRA和PGRB可以彼此相邻，并且位单元结构的第二侧。 每个通栅晶体管PGLA和PGLB可以与一对并联下拉晶体管中的一个的下拉晶体管中的一个连接。 类似地，每个通栅晶体管PGRA和PGRB可以与另一对并联下拉晶体管的下拉晶体管中的一个连接。

公开(公告)号：US20210012822A1

公开(公告)日：2021-01-14

申请号：US16508940

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amogh AGRAWAL ,  Ajey Poovannummoottil JACOB ,  Bipul C. PAUL

IPC: G11C11/16

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.