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    COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS
    3.
    发明申请
    COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS 有权
    具有不同通道高度的多个FINFET的通用制造

    公开(公告)号：US20160268400A1

    公开(公告)日：2016-09-15

    申请号：US14656671

    申请日：2015-03-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem AKARVARDAR ,  Jody A. FRONHEISER ,  Ajey Poovannummoottil JACOB

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417

    CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545

    Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.

    Abstract translation: 通常制造的FinFET型半导体器件具有不同（即，较高和较短）高度的整个或仅一些鳍片的沟道区域。 在只有一些翅片的通道具有不同的高度的情况下，源和下水道具有比这些通道高的公共高度。 不同的翅片高度是通过使一些翅片凹陷而产生的，并且只有通道具有不同的高度，差异是通过暴露每个通道的顶表面旨在更短，其他通道被遮蔽并部分地使暴露的 频道。 在这两种情况下，可以去除掩模，并且可以进行常规的FinFET处理。

    FIN PITCH SCALING AND ACTIVE LAYER ISOLATION
    5.
    发明申请
    FIN PITCH SCALING AND ACTIVE LAYER ISOLATION 有权
    FIN PITCH SCALING和主动层隔离

    公开(公告)号：US20150061014A1

    公开(公告)日：2015-03-05

    申请号：US14011125

    申请日：2013-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil JACOB ,  Murat Kerem AKARVARDAR ,  Steven John BENTLEY ,  Bartlomiej Jan PAWLAK

    IPC: H01L21/764 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

    Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

    WAVEGUIDE STRUCTURES
    6.
    发明申请
    WAVEGUIDE STRUCTURES 有权

    公开(公告)号：US20210055477A1

    公开(公告)日：2021-02-25

    申请号：US16549466

    申请日：2019-08-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yusheng BIAN ,  Ajey Poovannummoottil JACOB ,  Steven M. SHANK

    IPC: G02B6/125 ,  G02B1/00

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.

    FINFET WITH INSULATOR UNDER CHANNEL
    8.
    发明申请
    FINFET WITH INSULATOR UNDER CHANNEL 有权
    带绝缘体的FINFET通道

    公开(公告)号：US20150021663A1

    公开(公告)日：2015-01-22

    申请号：US13945627

    申请日：2013-07-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Murat Kerem AKARVARDAR ,  Jody A. Fronheiser ,  Ajey Poovannummoottil JACOB

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

    Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

    GRATING COUPLERS WITH CLADDING LAYER(S)
    10.
    发明申请
    GRATING COUPLERS WITH CLADDING LAYER(S) 审中-公开

    公开(公告)号：US20190310399A1

    公开(公告)日：2019-10-10

    申请号：US15945347

    申请日：2018-04-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ajey Poovannummoottil JACOB ,  Yusheng BIAN

    IPC: G02B5/18 ,  G02B6/34 ,  G02B6/30

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with structured cladding and methods of manufacture. A structure includes: a grating coupler in a dielectric material; a back end of line (BEOL) multilayer stack over the dielectric material; and a multi-layered cladding structure of alternating materials directly on the BEOL multilayer stack.

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