公开(公告)号：US09817927B2

公开(公告)日：2017-11-14

申请号：US14841037

申请日：2015-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guo Xiang Ning ,  Yuping Ren ,  David Power ,  Lalit Shokeen ,  Chin Teong Lim ,  Paul W. Ackmann ,  Xiang Hu

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5009 ,  G03F1/36 ,  G06F17/5081

Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.