公开(公告)号：US10600914B2

公开(公告)日：2020-03-24

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US20190259708A1

公开(公告)日：2019-08-22

申请号：US15898606

申请日：2018-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Hao Tang ,  Yuping Ren ,  Rui Chen ,  Bradley Morgenfeld ,  Zheng G. Chen

IPC: H01L23/544 ,  G03F9/00 ,  G03F7/20 ,  H01L21/66 ,  G01N21/95

Abstract: This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

公开(公告)号：US20200020531A1

公开(公告)日：2020-01-16

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US09672313B2

公开(公告)日：2017-06-06

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US09666476B2

公开(公告)日：2017-05-30

申请号：US14969154

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Yuping Ren ,  Duohui Bei ,  Sipeng Gu ,  Huang Liu

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/538 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

公开(公告)号：US10777413B2

公开(公告)日：2020-09-15

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US10566291B2

公开(公告)日：2020-02-18

申请号：US15898606

申请日：2018-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Hao Tang ,  Yuping Ren ,  Rui Chen ,  Bradley Morgenfeld ,  Zheng G. Chen

IPC: H01L23/544 ,  G03F9/00 ,  G03F7/20 ,  G01N21/95 ,  H01L21/66

Abstract: This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

公开(公告)号：US10002827B2

公开(公告)日：2018-06-19

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  G03F1/36 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US10923388B2

公开(公告)日：2021-02-16

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Yuping Ren ,  Paul Ackmann ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US10395926B1

公开(公告)日：2019-08-27

申请号：US15954736

申请日：2018-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Minghao Tang ,  Yuping Ren ,  Sean Xuan Lin ,  Shao Beng Law ,  Genevieve Beique ,  Xun Xiang ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. A mandrel line is formed over a hardmask layer, and forming a block mask is formed over a first portion of the mandrel line that is linearly arranged between respective second portions of the mandrel line. After forming the first block mask, the second portions of the mandrel line are removed with an etching process to cut the mandrel line and expose respective portions of the hardmask layer. A second portion of the mandrel line is covered by the block mask during the etching process to define a mandrel cut in the mandrel line.