Abstract:
A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.
Abstract:
Approaches for simulating a photolithographic process are provided. Specifically, provided is an optical proximity correction (OPC) model that includes kernel parameters corresponding to inter-layer activity and an etch process for a connecting via of an integrated circuit (IC). A resultant intensity is determined for a corresponding plurality of process variations corresponding to the interlayer activity and the etch process. As such, the OPC model considers both interlay activity and etch process.